This is a crude ISA for the cpu. 

The PHX8 has 16 "main" instructions encoded in the top 4 bits of the byte. Some of these also have an encoding in the lower 4 bits.

The main instructions are encoded as follows:

OPERATION CODE HIGH ENCODING:
------------------------------------------------------------------------------
    HEX   OPC    OP    DESCRIPTION
------------------------------------------------------------------------------
    00    nop    -     no operation
    
DATA TRANSFER:
    10    mov   D, S    move reg to reg
    2-    ld    D, M    load from memory to reg
    3-    st    M, S    store from memory to reg 
    
DATA OPERATIONS:
    4-    add   D, S s    add
    5-    adc   D, S s    add with carry
    6-    sub   D, S s    subtract 
    7-    sbb   D, S s    subtract with borrow
    8-    and   D, S s    logical and
    9-    or    D, S s    logical or 
    A-    xor   D, S s    logical exclusive or
    B0    shr   D, S      shift right
    C-    cmp   S s       compare unsigned
    
SEQUENCING:
    D-    jmp    A    jump
    E0    ret    -    return from jump
    F0    hlt    -    halt

------------------------------------------------------------------------------
D    Destination
S    1st Source
s    2nd source
A    Address
M    Memory Address

Instructions with a X- instead of an X0 are further encoded as:

OPERATION CODE LOW ENCODING:
------------------------------------------------------------------------------
    HEX   OPC     OP        DESCRIPTION
------------------------------------------------------------------------------
LOAD:
    20    ldi    D, #00h    load immediate into register
    21    ldz    D, L       load indexed zeropage 
    22    ldz    D, &00h    load immediate zeropage 
    23    lda    D, H:L     load indexed absolute 
    24    lda    D, &0000h  load immediate absolute 

STORE:
    30    stz    L, S       store indexed zeropage
    31    stz    &00h, S    store immediate zeropage
    32    sta    H:L, S     store indexed absolute
    33    sta    &0000h, S  store immediate absolute

ARITHMETIC & LOGIC:
    add, adc, sub, sbb, and, or, xor, cmp 
    X0    ALU    D, S s     perform operation with registers  
    X1    ALU    D, S #00h  perform operation with register and immediate value

COMPARE:
    C0    cmp    S s        compare register to register
    C1    cmp    S #00h     compare register to immediate
JUMP:
    D0    jmp   H:L         jump unconditional indexed absolute
    D1    jmp   &0000h      jump unconditional immediate absolute
    D2    jc    H:L         jump carry indexed absolute
    D3    jc    &0000h      jump carry immediate absolute
    D4    jv    H:L         jump overflow indexed absolute
    D5    jv    &0000h      jump overflow immediate absolute
    D6    jz    H:L         jump zero indexed absolute
    D7    jz    &0000h      jump zero immediate absolute
    D8    jn    H:L         jump negative indexed absolute
    D9    jn    &0000h      jump negative immediate absolute
    DA    jg    H:L         jump greater indexed absolute
    DB    jg    &0000h      jump greater immediate absolute
    DC    jl    H:L         jump less indexed absolute
    DD    jl    &0000h      jump less immediate absolute
    DE    ji    H:L         jump input indexed absolute
    DF    ji    &0000h      jump input  immediate absolute

------------------------------------------------------------------------------
H,L  High, Low:  Register Index
&    Address 8 or 16 bits
#    Immediate value

All in all the Processor features 46 instructions.

1 No Operation

10 Data Transfer

17 Arithmetic & Logic 

18 Sequencing 

---

Now to the Processor Status Flags. These are used for the conditional jumps and are calculated/ overwritten if a Arithmetic, Logic or an Compare instruction is executed. With exeption of one flag: The Input Flag (I).

This flag turns 1 if the Processor recives an 8 bit value from the input port. This flag prevents overwriting an old value in the "Input Register" (IN) if I==1.

STATUS REGISTER (ST)
------------------------------------------------------------------------------
Bit Order:    7 6 5 4 3 2 1 0
              C V Z N G L I -
------------------------------------------------------------------------------
C    Carry        =1 If a carry or borrow occurs (unsigned arithmetic)
V    Overflow     =1 If arithmetic overflow occurs (signed arithmetic)
Z    Zero         =1 If the Result is =0   OR   If cmp S == s (Equal)
N    Negative     =1 If the 7th bit is 1 (signed)
G    Greater      =1 If cmp S > s 
L    Less         =1 If cmp S < s
I    Input        =1 If Input is updated

THE FOLLOWING OPERATIONS UPDATE THESE FLAGS:
------------------------------------------------------------------------------
OPC    FLAGS
------------------------------------------------------------------------------
add    C V Z N
adc    C V Z N
sub    C V Z N
sbb    C V Z N    
and    Z N
or     Z N
xor    Z N
shr    C Z N
cmp    Z G L 

---

Im still unsure how many Registers I should use (8 or 16) since the more registers I have the more wiring, breadboards and multiplexers I need. But these registers are for sure to implement:

GENERAL PURPOSE:
    A    (at least 3 GPR) (1 for Arithmetic "A") (2 for indexing "X,Y")
    X    
    Y    
SPECIAL:
    SR    Status Register
    IN    Input Register
    OT    Output Register
    PH    Program Counter High
    PL    Program Counter Low

Every register is 8 bit wide and can be accessed by any instruction that deals with "adressable" registers.

Internal Registers like "Instruction Register" or "Instruction Sequencer" arent listed yet but i will get to them in another log.