• PHX8 - Memory Unit

    aephx • 11/07/2017 at 20:13 • 0 comments

    Today I have finished the Memory Unit.
    It can store 64KB of memory (16 Address bits, 8 Data bits).

    Its made out of 2x 32KB SRAM chips and 1x Hex Inverter Chip (to control the selection of one of the two chips and the Write signal).

    An Arduino with 2x 8bit Shift Registers is used to Read/ Write the SRAM.

  • PHX8 - Instruction Set Architecture

    aephx • 11/06/2017 at 18:37 • 0 comments

    This is a crude ISA for the cpu. 

    The PHX8 has 16 "main" instructions encoded in the top 4 bits of the byte. Some of these also have an encoding in the lower 4 bits.

    The main instructions are encoded as follows:

    OPERATION CODE HIGH ENCODING:
------------------------------------------------------------------------------
    HEX   OPC    OP    DESCRIPTION
------------------------------------------------------------------------------
    00    nop    -     no operation
    
DATA TRANSFER:
    10    mov   D, S    move reg to reg
    2-    ld    D, M    load from memory to reg
    3-    st    M, S    store from memory to reg 
    
DATA OPERATIONS:
    4-    add   D, S s    add
    5-    adc   D, S s    add with carry
    6-    sub   D, S s    subtract 
    7-    sbb   D, S s    subtract with borrow
    8-    and   D, S s    logical and
    9-    or    D, S s    logical or 
    A-    xor   D, S s    logical exclusive or
    B0    shr   D, S      shift right
    C-    cmp   S s       compare unsigned
    
SEQUENCING:
    D-    jmp    A    jump
    E0    ret    -    return from jump
    F0    hlt    -    halt

------------------------------------------------------------------------------
D    Destination
S    1st Source
s    2nd source
A    Address
M    Memory Address

    Instructions with a X- instead of an X0 are further encoded as:

    OPERATION CODE LOW ENCODING:
------------------------------------------------------------------------------
    HEX   OPC     OP        DESCRIPTION
------------------------------------------------------------------------------
LOAD:
    20    ldi    D, #00h    load immediate into register
    21    ldz    D, L       load indexed zeropage 
    22    ldz    D, &00h    load immediate zeropage 
    23    lda    D, H:L     load indexed absolute 
    24    lda    D, &0000h  load immediate absolute 

STORE:
    30    stz    L, S       store indexed zeropage
    31    stz    &00h, S    store immediate zeropage
    32    sta    H:L, S     store indexed absolute
    33    sta    &0000h, S  store immediate absolute

ARITHMETIC & LOGIC:
    add, adc, sub, sbb, and, or, xor, cmp 
    X0    ALU    D, S s     perform operation with registers  
    X1    ALU    D, S #00h  perform operation with register and immediate value

COMPARE:
    C0    cmp    S s        compare register to register
    C1    cmp    S #00h     compare register to immediate
JUMP:
    D0    jmp   H:L         jump unconditional indexed absolute
    D1    jmp   &0000h      jump unconditional immediate absolute
    D2    jc    H:L         jump carry indexed absolute
    D3    jc    &0000h      jump carry immediate absolute
    D4    jv    H:L         jump overflow indexed absolute
    D5    jv    &0000h      jump overflow immediate absolute
    D6    jz    H:L         jump zero indexed absolute
    D7    jz    &0000h      jump zero immediate absolute
    D8    jn    H:L         jump negative indexed absolute
    D9    jn    &0000h      jump negative immediate absolute
    DA    jg    H:L         jump greater indexed absolute
 DB jg &0000h...
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