In the project-description I try to explain the non-discrete nature of magnetic media, and do-so quite poorly. Here's a simpler example:
A 74595(?) shift-register can take in a serial stream of bits, and convert that serial stream into 8 parallel output bits. There are 8 discrete positions for a bit to be stored.
Similar to any digital-memory, like SRAM, etc. Each bit is discretely positioned on the output of some 1-bit-wide logic circuit, e.g. a Flip-flop (SRAM), or a capacitor tied to a logic gate (DRAM). Again, that same circuit is repeated for each and every bit.
In the case of a shift-register, we essentially have an 8-bit SRAM whose input is serial and output is parallel.
So, say you load the serial bitstream 01011001 into the shift-register's input, then the 8 discrete outputs will each show one of those 8 bits.
But now, what when you change that input bitstream to have a tiny pulse of '1' between the two zeros? It's not like, suddenly, a new output circuit/pin will be inserted between bits 6 and 7 to show that '1'.
This may seem ridiculous to harp on, but the fact is that magnetic media, signals sent down wires, even RF and optical systems are more-often-than-not treated as discrete-time systems just like that serial bitstream fed into that shift-register.
That extra '1' bit, discussed earlier, is considered a glitch in most storage and communication systems. Similarly, any value-change on that data stream at any time *other* than those discrete bit positions... (TODO: timing diagram). These, too, are considered glitches in most current systems (aka jitter).
Frankly, I think that's a tremendous setback to our technological progress (maybe that's a good thing?).
Similar to that 'glitch', even more similarly to that jitter, is the PWM-system I've designed, here... Feeding that *directly* into a shift-register seems a bit ridiculous... It won't work *at all* with the original MFM or RLL system, its shift-registers nor timing constraints. But it could work with the same (slow) technology available at the time, and so much easier with that available today.
Continuing with its seeming ridiculosity: For it to work properly fed into a discrete-time system like a shift-register (similar to the MFM design of the era), the PWM-Nibble--5us long, with 16 values stored in the middle 1us--would require a shift-register at least 48 bits long (more like 72!). And that shift-register would have to be 16 times faster than those in the original MFM/RLL system. Further, Only 16 of those 48 shift-register outputs would contain data. And that data, when packed in binary, would easily be represented by 4 shift-register outputs.
Speed-wise, as described in the project description, this system *could* have been achieved with the slower technology of the era... Using similar techniques as a 100MS/s oscilloscope with 50MHz ADCs, alternately taking samples. Or, much easier, by using timer-counters to measure the width of the pulse... As I recall, even the original 74163(?) could run at 16MHz. But, either way, there would be quite a bit more logic involved, and that wasn't cheap in an era where a Floppy Drive cost $200.
So, absolutely, this method seems *completely* ridiculous as a means of storing or sending binary data.
Except that magnetic media, fiber-optics, RF, etc. are *NOT* discrete-time systems, despite regularly being treated that way.
So, now we exist in an era where FAST DSPs exist, an era where FAST shift-registers can be packed in by the thousands in a tiny cheap piece of silicon... And yet, we're still treating things like magnetic media, optical media, and coaxial media as though they're discrete-time and we need to pack on them as many binary bits, in discrete binary forms, each occupying some discrete amount of time or space.
I think we've missed something.
This PWM-nibble method I've come up with may be still discrete-time, cramming 16 values in 1us. But, it relies *significantly* on the fact that the magnetic media is non-discrete when compared to the normal MFM or even RLL 'bits' usually stored, individually, in *discrete* bit-wide spacing. And the PWM system ideally does so WHILE maintaining the discrete-value benefits of our so-reliable digital systems today.
That's the idea.
And there's no reason to limit that idea to all-but-extinct floppy drives.
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OK, as an aside, it *just* occurred to me how much this system is similar to my project AVR-LVDS-LCD (todo:link github?)... Wherein I use an AVR's Fast-PLL-based timer to create PWM signals that correspond to serial data-streams to drive an LVDS/FPD-Link LCD.
Not a big deal, I just thought it was an interesting thing that these projects are so similar, yet seem so different.
There, I've managed to squeeze 48 colors, pretty close to evenly-spaced on a color-map, out of PWM signals fed into a *serial* input expecting sequential binary data-bits. (Todo: timing diagrams!). As well as sending proper pulses for Hsync, Vsync, and Data Enable... And this from the PWM-output of an AVR running at 1/4 the speed.
PWM FTW!
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You might be interested in the datasheet for a 4517 (from the famous 4000 series) shift register... I have a copy if The Great Goog does not feel like obliging ;)
(I find that NXP/Nexperia datasheets are particularly excellent, BTW...)
Also: I shall leave aside to even more unmannerly folks than me, meditations and perhaps the odd soliloquy with regards to the phraseology of "indiscrete timing" ;)
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meh, I knew it was wrong as soon as I wrote it.
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Wrong is the wrong word, really... "indescrete" is accurate and precise, it just invokes additional contexts which may or may not be relevant.
TBH it mostly just makes me chuckle.
Did you see what I wrote about that datasheet? That might be useful...
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Whoa, what a weird chip! Already geting ideas for its use here and elsewhere.
yeah, them engineers, mathematicians, scientists, etc. love mangling English so that once-loaded phrases have new meaning. Plenty to ponder in that.
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Glad ta help as always :)
...but there's the 48+ stage shift register you ordered in your article, you know... and to think they probably had it "back then", too... ;)
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Indeed, I caught its being a darn-near perfect-fit. Incredible!
Have been pondering the next stage of the circuit. I think a second shift-reg, 16 bits long, with individual outputs gets tied to the 4517's bit31 output. That guy's outputs fed to a (couple) decade-to-binary converters. Alternatively a 4-bit counter in there somewhere might do the job nicely.
Alternatively-still, am pondering the ability to auto-sync the clock with two sequential "PWM-Start" edges, assuming (in that design) they're precisely 5*16 'ticks' apart. I think the digital-side of such syncing could benefit greatly from the 4517 and a couple additional latches.
Presently, that design (precise 5*16) is on-hold, due to my software's overhead-constraints on my lowly 16MHz uC. Here, the parallel-nature of discrete-logic, even of that era, might 'win' over the serial-processing ability of a single-cycle-per-instruction MCU with dedicated on-chip peripherals several generations newer!
Interesting ponderances.
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...everything new is old again...? :D
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