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NOP.PLD.txt
Dual-purpose 22V10
1. Forces NOP codes on the data bus during video access cycles.
2. Read the keyboard data.
22V10
text/plain -
1.68 kB -
08/25/2023 at 20:31
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DECODE.PLD.txt
The memory map decoder and 3-bit tri-state counter for character row generation.
22V10
text/plain -
2.48 kB -
08/25/2023 at 02:16
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SHIFT.PLD.txt
The shift register for video generation.
Half latches the character data D0-7 to drive the character ROM address lines later.
Half latches the character data D0-7 into a shift register to drive the video signal.
ATV750.
plain -
3.27 kB -
08/25/2023 at 02:17
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HSYNC.PLD.txt
The horizontal sync generator for video generation.
ATV750
Contains the SLOW mode timing generator.
The divisor is 208, because 3.25 MHz/208 = 15625 Hz line frequency.
For square-pixel-40-column-PAL 14.75/2=7.375, the divisor should be 236.
For square-pixel-40-column-NTSC 12+3/11/2=3.068 MHz and 15750 line rate, the divisor should be 195.
plain -
3.24 kB -
08/25/2023 at 02:17
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KEYFIX.PLD.txt
The Keyboard remapper. Not needed if you have a ZX81-compatible keyboard matrix.
ATV750
text/plain -
2.90 kB -
08/25/2023 at 02:16
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K8082.pdf
My best guess at the wiring.
Adobe Portable Document Format -
45.74 kB -
01/12/2018 at 03:05
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ZX81_in_SPLD_chips.zip
HTML documentation. Start page is ZX81_SPLD.htm
x-zip-compressed -
113.32 kB -
01/10/2018 at 23:36
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Keith