The Quub

Mission creep has set in and I've added a lot of features. Here is a 3D render of the latest version of the main PCB.

Almost as soon as I received the last PCBs I had a few ideas for some changes. So I'll be getting new ones made and won't be using the last ones. They cost almost nothing to make these days so might as well get it as right as possible eh?

This project started about 10 years ago and has had more starts than Phar Lap (Aussie joke). Yet more processor PCBs made recently. The core processor has been changed to a Raspberry Pi Pico, partly because it has castellated pads so it can be soldered directly to the QUUB board, and partly because I think that there is a much larger following and body of work out there for that particular processor.

Here are five of them stacked, giving some idea of where the QUUB name came from  Of course one would not stack five MCU boards, I just wanted to check the mechanical aspects of the idea.

The PCB v1 has been in use for a while now and some support code has been written to remap a few of the default Adafruit pins to get a second UART etc.

During the course of this I had many new ideas and have modified the PCB substantially. It's almost ready to be fabbed as v2 now, here's a 3D render of the new look.

NOTE: Circuit boards called "walls" can be soldered at right angles to the main PCB on the four edges, these have access to all the backplane signals so can have active electronics and connecters to facilitate IO, or just be blank to form the sides of a box. These walls are designated as per the cardinal points of a compass, N, E, W, and S.

With all four walls in place and the addition of a top PCB the design is essentially "self enclosing".

The "stackplane" is now three Arduino-style socket strips, one is 22-way with most of the logic signals and two are 3-way that mostly carry power.

The expansion bus has been extended to include most of the backplane signals. The expansion module now sits at the same height as the Adafruilt CPU module. Normally this expansion module would be used for small functions that don't justify an entire stackable daughter board, such as an RTC or micro SD card. It could also be used for IO like a serial port or more STEMMA-QT/QWIIC interfaces as it has some access to the west and east walls and even the south wall if it is designed in an L shape.

There is now hardware decoding for six slave select signals, one for each wall, one for the expansion module, and another for the backplane. Thus up to six devices can share signals such as the SPI interface. Alternatively up to 16 stackable and addressable boards are allowed for and each such board can provide a vectored interrupt with a protocol for this being largely defined.

Two STEMMA-QT/QWIIC connecters have been added, this is fast becoming a standard so it makes sense to include them. I always planned to have a quad buffered interface for this and still will, but these two connecters allow the use of STEMMA-QT/QWIIC modules right off the bat.

Another addition is dedicated pins on the debug header, these can be used as scope triggers or for other high-speed measuring. Also internal data variables can be bit banged out these pins and read on a scope. Code has been written to do this. Naturally a standard ICE debugger for an ARM can be used as well and I have plans to design a debug board with some useful features.

Finally both the debug and expansion headers allow for the direct plugging in of a common 0.91" OLED I2C serial display, either for debugging or general UI purposes.

The design files have just been uploaded to JLCBPCB, this is the base board to hold the Adafruit CPU module. The tabs on each corner are to locate the side "walls" that can house more circuitry and/or physical IO connectors.

This is the new design. After a few years of inaction I've come up with a modified design that is much simpler and yet more powerful in most ways.

The original design only had a single solder-on side, this new design has four, all of which can house electronics and/or connectors for IO interfaces.

Another big change is the processor. Despite the fact that I love their chips and tool chain, after total lack of support from NXP I've gone with an off-the-shelf design in the form of a tiny carrier board with a ATSAMD51 Cortex M4. This is an Adafruit product that has good support and is Arduino ready. Therefore I will spend almost no time debugging the processor electronics and fighting with the development toolchain only to wind up with something that nobody will want to use because it's not "Arduino inside".

Of course, as the processor is on a carrier board, and the backplane is very generic, a new processor version can be designed at any time and just plugged in.

This project has languished for a long time but I think I will resurrect it. 

The format will change but still be similar in many ways, with stackable boards and solder-on front panels. The main difference is that the new design uses an LPC1549 ARM processor and has built in RS485 networking using a protocol I am designing called R3N (Robust Redundant Ring Network).

Why bother when you can run Linux and WiFi or Ethernet on a board 1" square these days? I dunno, I just like doing this stuff and I can see uses for it.