Hey there,

I just remembered that the JTAG header is still missing from the schematic; I will add it promptly. In the meantime, I'm proceeding with the layout of the board, it is going to be a bit though because I'd like to keep the Analog ground plane as separate as possible from the Digital ground plane so to have the best performance when using analog pins (which shall be connected to stuff powered from VDDANA and grounded to GNDANA), and also because using 0603 caps on such a small board makes it difficult to keep decoupling caps as near as possible to the chip while also not "walling" too many pins; I'll try to apply local ground planes under critical components (main chip, clock, analog stuff) and star them near the LDO.

As always, please check the repo for the most up-to-date version of the project files.

Cheers, Mick