ChristophIt's very cool that xilinx give us free software (Vivado) that we can use to simulate our designs. BUT there are some gotchas. When I tried to simulate writing to/reading from RAM it seemed that nothing worked as intended, until I simulated for a longer time (> 100 ns). After skimming the datasheets, RAM usage guides, I finally opened the "Vivado Design Suite User Guide", where I found this:
"Apply stimulus data after 100ns to account for the default Global Set/Reset (GSR) pulse used in functional and timing-based simulation."
This boils down to: RTFM. Ah well...
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WTF... Let me guess : no warning ?
I'll stick to the aging ProASIC3 for a little longer while, not just because I have some stock but also because I'm used to this family, I can WORK with them and they deliver what I need.
I'm excited by Antti's work and awesome results but I'm far from sold to Xilinx yet :-D I'd love to see his SF2/Igloo2 boards soon ;-)
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of course no warning! Also to clarify: I use vivado only for simulation of simple circuits. Dipsy uses a lattice chip, so I can't simulate for that
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For sim I use GHDL, of course ;-)
Its VHPI interface makes it easy to add "special devices" for actual I/O, I can even map a framebuffer to my actual screen :-D and it's all under GPL license...
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I did use Xilinx ISE for simulation soft processors that i wanted to implement in Actel FPGA's. All the tools have their GOTCHA's !
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