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New CPU design, mass storage problems
04/02/2017 at 20:40 • 0 commentsMy old N-Series CPU design is an incredibly inefficient CISC architecture that is no doubt super slow just due to the number of clock cycles and unnecessary memory accesses per instruction. I'm going to create a new architecture that supports more memory and is hopefully much faster (133 Mhz???).
The reason I haven't updated this project much in so long is because I ran into some mass storage problems. The FPGA board I'm using has 3 places to store non-volatile data. After an attempt at every. single. one, I needed a break. Its a bit frustrating when not even parallel NOR flash will work right, after trying SPI eeprom and the FPGA's own non-volatile storage. Any advice would be appreciated, by the way.
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PS2 Keyboard interface working
10/02/2016 at 09:34 • 0 commentsI finally got the keyboard to work. PS2 interface working nicely and printed keystrokes on the screen. I was getting trouble when using my FIFO as a hardware keyboard buffer, needed to fix some timing. Also now working on a sort of datasheet for my CPU, I'll make docs for the entire system when it has disk support.
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Video working, and new interface too!
08/01/2016 at 01:32 • 0 commentsI eventually decided that putting graphics on the FPGA would not be a good idea for two reasons:
- The CPU would be drawing the graphics
- I would only have enough memory for 8-color 256 x 256 pixel graphics
This just wasn't going to be enough, so I brought in my Parallax Propeller chip. The propeller is perfect because it runs on 3.3v, has great ability to generate graphics, and will do the video processing for the main CPU. I set it up with UART at 115200 bps and connected it to my FPGA. It took some trial-and-error to get some signs of life from my Propeller saying that it was getting a transmission, then from there I got a Hello World program working.
From here I decided that between the FPGA and the other devices there will be a standard protocol using UART. Don't worry, the UART won't be as slow because there are hardware FIFOs allowing a program to run without waiting for data to finish transmtting.
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Redesigned layout in ISE
08/01/2016 at 01:04 • 0 commentsI decided things should work better if I broke my project into mini projects, tested them, and included them into the main project. This seems to have worked very well. I also made this change so that if I made another version of the design in another ISE project, It would be easy to make backwards compatible and\ work together.