I figured if I had the GPU use the SDRAM, and let the display scan out of SRAM, I could avoid bottlenecks for display scanout. But there's still contention to copy from SDRAM to SRAM when the framebuffer is dirty, and if I let the LCD scanout have bus priority it takes a good 5 seconds per frame update..

Going to try inserting a FIFO into the display scanner that charges from SRAM,, with the display running at a fraction of the speed of the memory bus.

Update: With a scanline buffer it's significantly faster but still has a bit of a boxcar effect.

update: fixed the tearing a bit: