The Arithmetic and Logic Unit (ALU) adds, subtracts and performs boolean operations on the operands, so it's more or less the heart of any computer.

This project has two versions: the prototype stage that mixes 3.3V and 5V chips, then the final circuit with 3.3V chips only (for lower power).

Finding ALU chips was a weird experience but it was not too hard. I did not consider implementing a full adder with individual logic gates, it would be really too hard, slow, error-prone, confusing...

I found several 74F381 online, for about 1.5$ each.

These are fast 4-bits adders with AND/OR/XOR. However, despite a carry input, there is no carry output for cascading.

/Generate and /Propagate are available but they require other support chips. The Datasheet from Fairchild mentions the 74F382 but I have no idea if/how I can find one...

Being a F-type chip, the power consumption is not negligible : about 60mA each (like one TIL311 and 4 are needed). The F-type signals work with current, while the HC work with voltage, so pull-up resistors are needed (more power draw).

It's also a pretty rare part, now, with no SMD version in sight.

By chance, I found a few 74LS181 in an old local store.

Can you believe that they have been manufactured more than 30 years ago ? How long have they been waiting in a box/tray/shelf ?

The '181 has a carry output (inverted) so it's easily cascadable. The function set is quite flexible so it's often used for DIY projects. But it's not an option for the final version...

SMD versions of the '181 are too rare and too expensive. DIP versions are in the "a few dollars" range so a 16-bits ALU costs more than 10$. Luckily, I have found another more advanced circuit: the IDT7381 16-bits ALU.

It's a PLCC chip so it is "mostly" SMD (on the "thick" side of "thin") but the cost of a 16-bits slice is about the same as a 4-bits only '181. The operations are identical to the 74F381 but in CMOS and the Carry Lookahead is integrated (there are outputs but one chip is enough). It's pretty fast, the sum/difference is output in less than 30ns. Power consumption is lower, too, worst case 60mA for 16 bits.

But this part is also obsolete, available in limited quantity, and it's a 5V part. There are one or two equivalent products but I wouldn't bet on their long-term availability. At $3/pc, it's great for hacking stuff but there must be a better way.

It doesn't look possible to reach $1 for a 16-bits ALU (with added constraints of decent speed, ultra low profile and 3.3V supply). However around $2, there are more possibilities using CPLD/EPLD. The data use 16×3 bits, 48 input/output pins, plus all the control and status signals, at least 68 pins are required and the cost is still high.

But I have found low density FPGAs: the A3P030 is the smalled of the family with an easy to solder TQFP100. It's more or less equivalent to a 256 macrocells CPLD (768 LUT3), works at 3.3V, and I have all the hardware and software tools. I can even reuse source code from previous YASEP implementations.

It's weird that the project has gone "full circle" and returns to the chips it tried to avoid. However, the ALU is a special kind of circuit that is very hard to do well and cheaply. An exception to the rules can help progress while respecting the other design constraints. The A3P030 doesn't have SRAM blocks, a PLL or some other features from the larger chips so there is no risk of feature creep.

A "discrete" version of the ALU would be implemented in a different project. Because it uses many types of logic gates, it will be hard to find suitable and cheap ICs. Unlike the SHL unit, the structure is not very regular and the design would be very hard. Several years ago, I have fiddled with a 32-bits adder at the gate level and it was not a pleasant experience...

Update (2016-01-06):

I found some 74HC283 :) It's a plain dumb 4-bits adder with Carry In and Carry Out, straight-forward to cascade. Quite slow but convenient and no voltage translation chip is needed, since it works with the same 3.3V levels as the surrounding circuits.

The boolean operations (AND/OR/XOR) require external chips but that's not a real problem.