I decided rather than just sending a packet header through the network I thought I would write some assembly to create a full packet.

Lo and behold the core initially started behaving very oddly.

After looking into it I discovered an issue where there was a stall coming into the Prefetch at the same point that there was a starvation in the Prefetch horizontal FIFO.

I fixed this and then the program successfully ran, I still need to make the Prefetch significantly more efficient.

So with this in mind I examined the state of the interconnect. The interconnect is not complete with respect to the roting logic understanding that the matrix is circular in all directions so I expected the top plane packets to go 'down'.

It got as far as the next plane and then stopped.

Seemed odd as the other packets seemed to have got through.

Debugging found three sets of problems.

1. The old inversion of the direction tables (this should be in the common library !) so it wasn't going to go the right way once it got to the next level.

2. The Arbiter has three sets of arbitration, Priority Select, Round Robin above and below the last Selection. The Priority Select appeared fine, it selected the zero priority packet. However as the packet was a zero priority it is constructed to select other zero priority packets in a round robin sense. This ensures that things are fair.

So I spotted in the code that the trees to perform the latter selections were not set up correctly at the base, that one had had the 'x' 'y' swapped and that the inner loop started at 1 rather than zero (tree creation in VHDL is interesting).

Once this was done the packet flowed all the way through the matrix to it's bottom core.

I also observed that the 'send data' line was also still active after a packet had started to be sent. Not good as this would mean data loss !! This is now fixed.

So fixed a bug in the core, fixed a bug in the net ! Good work I feel !