I am in the middle of writing a Non Blocking Interconnect. So far have written a programmable Master Decode Block and now just completed the Master to Slave Arbiter block.
So far Trinity has sat insided a very simple memory system. The problem with that is that it only allows one Master and prohibits the use of DMA to shuffle data around as this would have to be a Master.
The reason why I mention Non Blocking is that if you had a blocking interconnect you could not have two masters accessing two different memories which would slow things down.
How will this improve things, well as mentioned it will allow a DMA block to be used, this would mean that in the Multicore environment we could relocate some code/data that has arrived tosomewhere else for example. Or shuffle some data into the payload area in preparation to be transmitted back.
I've managed to re-use some code for the Arbiter in respect to the Finding the First One execute block in the Execution unit (reaping the rewards :) ).
The initial DMA will be very simple, just a word to word movement for speed.

The next block to write will be an interrupt handler. Trinity has the concept of a Processor State Level. Should the core be dealing with an Exception or an Interrupt it can increase this level to a determined value. This can then be used to triage out a further interrupt if it's associated programmable 'Priority State Class' is below that of the present Processor State Level.
Say for example Trinity is dealing with a UART interrupt. It may place its Processor State Level to 1. However suddenly a really time critical interrupt comes in, this has to be dealt with as soon as possible and Trinity come back to servicing the UART interrupt because it is less important.