It's been a while since I synthesized anything relating to Trinity.
I thought I would however take the Dual Core Complex and build it.

When it was synthesized back in 2011 it was around 13000 Logic blocks, lot's of room.

Now the Dual Core Complex, the Timer, PIO, Interrupt, the Memory Interconnect has consumed the Cyclone III FPGA, it's at 95% fill !

I spotted some long paths in there which I wasn't expectiing so managed to find a way of reducing those. Also added the PLL to give a clean clock.

The timing reports advise that I can get up to 30 MHz but I've got the clocks down at 25 MHz.

Yes it would be great to get up higher that this but at 95% fill I am pleasantly surprised it goes this fast.
There is a basic rule of thumb, once you start to get above 60% fill timing becomes harder, the more fill the harder. This is because the logic can't all be placed next to each other and the more logic requires more routing within the FPGA, this is a continuous issue with FPGA work.

Because I'm not doing this professionally I don't need to get it up to 100 MHz, 25 MHz is fine.

One thing did appear to be quite odd. The General Purpose register file appeared to be about 1500 Logic element (1024 registers), however the Control and Status registers was at ~ 20k Logic elements which seemed to twice the expected area. This is something to examine.

There is also something that is quite good to know, I appear to have only used 10 % of the available SRAM that is onboard which means that I can possibly expand the memories from their 4 KB blocks, however the routing may become an issue.

I have been looking at the tools again and have discovered that there is a methodology of reprogramming the memories without having to go through the whole process of resynthing the FPGA. Just get the updated if files and then run the tool and re -assemble. So all good.

A few days ago I was chatting to a friend with regards to documentation in Software and was astonished as to there being little done in comparison to Hardware. Well that has come back to bite me, I've been looking at some assembler I wrote six years ago attempting to update it for the new Dual Core complex and there aren't even any comments !!

Mea Culpa !

I intend to get the code converted and run up the LCD that is on the dev board that I have.
By the looks of it there needs to be a bit of preamble which fixed me and then we are into ASCII which is good news.

What next, well I think I need to get some kind of RS232 input in there so I can communicate properly.
This is not going to be as trivial as it sounds.

There is an RS232 port on the board but I need to workout how to connect to it, put a RS232 block within the code and then put in support to use it.  Open ended projects are cool in this respect.