I've just completed the update to the system so that it has a Dual Port RAM that can be accessed by the Instruction and Data Busses for each node. I could have used a Single Port RAM but this has two draw backs.

1. I would have to put in an arbiter, and from previous experience of Harvard Machines you give the Data Bus priority.

2. It doesn't keep in the ethos of the system, why delay something when you can make it go faster.

It is also easier to just plug in a dual port memory block and go from there.

I need to test the set up which will happen at some point this week.

As an aside I have well an truly blown the 10,000 line limit for the Modelsim Altera Web Pack simulator. It's now amazingly slow, but I don't have the money to buy a full blown license so I just have to make do and get the 'job' done.
How typically British :).