Let's estimate how many transistors are required for this clock project.

So far we have the following chart :

• Inverter : 2 T
• NAND, NOR: 4T
• OR, AND : inv+Ngate= 6T
• D-FF: 16T

Actually the whole system is mostly made of D-FF:

• Each of the 15 stages of the 32K predivider is made of one D-FF, that's already 240 transistors !
• Each N-state Johnson counter has N/2 D-FF, and there are 16+16+14=46 stages or 23 DFF, 368 transistors...
• Each N-state Johnson counter has a NAND2 gate, 46×4=184 FET
• Each LED segment has a N-FET inverter, totaling 7×6=42.

The quantity of transistors so far is 834 with a little bias toward N-FET. I haven't even counted reset gates or stuff like that. This is more than I expected and I'm looking for ways to reduce this number.

• There must be an optimisation for the binary divider. A BJT version uses only two transistors but the bistable configuration uses resistors and capacitors, so "it's cheating".
• I'm thinking about a cascaded Johnson topology with a "master" Johnson counter (made of typical DFF) which outputs clock pulses to "slave" Johnson counters made of smaller latches.