PCIe Gen 5 NVMe on SBCs: Why Thermal Throttling Starts in the Power Tree

A PCIe Gen 5 NVMe drive can deliver impressive storage bandwidth on a single-board computer, edge gateway, or compact AI system. The design challenge is not only the connector and differential pair. The SSD creates a fast load on the 3.3 V rail, generates heat in a small enclosure, and can change its power state faster than a simple regulator and thermal pad can follow. Reliable storage requires a power tree and thermal plan built around the drive's workload.

What makes a Gen 5 NVMe drive different?

PCIe Gen 5 increases the signaling rate and often raises the controller, NAND, and thermal-management demands. The drive may draw modest current while idle, then jump during sequential writes, garbage collection, encryption, or a high-queue-depth read. A drive that passes a short benchmark may throttle during a long capture or model-building job.

Start with the storage rail map. Record the input voltage range, peak current, inrush behavior, reset threshold, power-state transitions, and allowed ripple. Add the host processor, memory, Ethernet, radio, fan, and accelerator to the same map. A storage test rarely runs alone in an edge system.

The power-management references at MOZE Electronics PMIC resources help structure the choice between a dedicated converter, a shared system rail, a load switch, and a monitored enable path. The design should state which event causes a reset and which event causes a controlled storage shutdown.

Which power path should feed the SSD?

The 3.3 V path should have a low-impedance route from regulator to connector, with local bulk and ceramic capacitance close to the SSD socket or module. The converter must handle the fast load step without excessive droop, overshoot, or unstable behavior at light load. If the board supports multiple storage options, calculate the worst case rather than designing around the lowest-power drive.

A shared 3.3 V rail can work when the processor and drive have compatible transient behavior. It becomes risky when the processor enters a high-current state while the SSD begins a write burst. A dedicated post-regulator or load switch can isolate the event, but it adds conduction loss, current-limit behavior, and another startup condition.

Ceramic capacitance needs a DC-bias review. The MOZE ceramic capacitor selection guide is useful when the rail voltage, package size, and temperature reduce the effective value below the marking. Place the smallest effective loop at the connector, then add bulk capacitance for lower-frequency energy storage.

How should PCIe power and data routing share the board?

The PCIe pairs need a controlled reference, while the power path needs enough copper and via capacity for current spreading. Do not let a high-current plane neck pass beneath a sensitive pair if it creates return-current movement or local impedance variation. Do not route the switch node from a regulator through the same area as the connector launch.

Use a stackup with known dielectric thickness and a clear return path. The guidance at MOZPCB impedance-control PCB design helps connect the fabrication stackup to the PCIe connector, via transition, and loss budget. Confirm the actual board thickness, copper weight, resin content, and etch capability with the fabricator.

Keep the differential pairs away from the inductor, switch node, and high-current return neck. If the SSD is on a small carrier or flex, define the connector pinout so ground pins surround the high-speed lanes and the power pins have enough current capacity. A short trace can still fail if its reference plane is interrupted.

Why does thermal throttling look like a software bug?

Thermal throttling changes performance gradually, while a power droop can cause an abrupt reset. Both can appear as a failed benchmark. Log the SSD temperature, controller state, host rail voltage, write queue, and throughput in the same test. If throughput falls at a repeatable temperature, inspect the heat path. If the drive resets at...

A Battery Board Is Three Systems Sharing One Current Path

A small battery-powered board often combines a charger, a protection circuit, a regulator, and a processor. On the schematic they can look like separate blocks. In operation, they are three tightly coupled systems: energy enters, energy is stored, and energy is converted into a load rail.

Charging current is not system current

If a USB-C input supplies a battery charger while the product is running, the input current may be divided between the load and the battery. A charger that is sized only for the nominal battery charge current can behave badly when the load changes state.

Write the current paths for at least these states:

• USB present, battery charging, load asleep;
• USB present, battery charging, radio transmitting;
• USB removed, battery powering the load;
• battery near empty, regulator at its worst dropout margin.

The board should have an intentional policy for each state. Otherwise, a radio burst can reduce the system rail while the charger is simultaneously trying to regulate the battery.

USB-C starts at the connector

For a basic sink, the CC pins need the correct pull-down behavior. VBUS also needs input protection, current limiting, and a clear path to the charger. Connector shield, high-speed data pins, and power return should not be treated as one anonymous net.

The battery charger and buck-boost schematic example is a useful reminder that the charger, converter, USB-C network, and battery nets must be reviewed together. Use it as an architectural reference, not as a drop-in design.

The converter sees the battery’s entire life

A buck-boost regulator may produce a stable 3.3 V from a battery that moves above and below the output voltage. Its difficult cases are often at the edges: cold-start, low battery, maximum radio burst, and a nearly empty battery with increased internal resistance.

Check the converter’s input ripple current, inductor saturation current, switch-node layout, and feedback routing. The required capacitor value must be evaluated at bias and temperature, not copied from the nominal marking. A practical starting point is the DC-DC converter, followed by the exact regulator data sheet.

For the input and output capacitors, compare dielectric and package options in the TDK component, then verify the chosen part’s DC-bias and ripple-current behavior.

Layout decides whether the blocks cooperate

Keep the charger’s hot loop compact. Keep the converter’s switch node away from the antenna, sensor, and feedback trace. Route battery current through copper that can carry the pulse without excessive drop, and place the voltage-sense connection where it measures the intended node rather than a connector-side approximation.

The PCB impedance-control guidance is relevant when USB high-speed traces or RF lines share the board, but the same layout discipline applies to the power tree: define the return path and do not let an uncontrolled current loop cross a sensitive reference area.

Verify with a state table

During bring-up, log input voltage, battery voltage, system-rail voltage, charge status, and load current. Repeat the test with the battery at several states of charge. A board that passes with a bench supply can still fail with a battery because the source impedance is different.

Use the component derating calculator for a first-pass check on resistors and protection parts, then confirm the manufacturer curves. Inspect the assembled board for capacitor orientation, connector solder coverage, thermal pads, and the correct charger variant through the PCB assembly workflow.

The best battery board is not the one with the most blocks. It is the one whose current paths, transitions, and fault states are explicit.

I2C Pull-Ups: The One Resistor Choice That Changes Your Whole Bus

I2C looks simple because it needs only two signal lines. The simplicity is deceptive. SDA and SCL are open-drain buses, so the pull-up resistors, trace capacitance, device count, cable length, and voltage levels all determine whether the edges are fast enough and whether the bus can sink the required current.

Why the resistor is a timing component

When a device releases the line, the pull-up resistor charges the total bus capacitance. The rising edge is approximately RC behavior, so a smaller resistor gives a faster edge and a larger resistor gives a slower edge. But a smaller resistor also increases the current every time a device pulls the line low.

The bus capacitance includes pins, package parasitics, traces, connectors, level shifters, and cables. A value that works on a short breakout board may fail when the same sensor is moved to a remote enclosure.

Check both limits

The pull-up must be small enough for the required rise time and large enough that the sink device can pull the line below its low-level voltage. A simplified low-level current is:

IOL ≈ VDD / Rpullup

Compare that current with the device’s specified sink capability, including voltage drop and temperature. The fastest possible bus is not useful if the sensor cannot pull the line low reliably.

For a first estimate, calculate the bus capacitance and use the relevant I2C rise-time requirement. Then validate with a scope at the farthest device, not directly at the controller pins.

Watch for duplicate pull-ups

Every breakout board may include its own pull-ups. Three modules can quietly put three resistor pairs in parallel. The effective resistance becomes lower, the low-level current rises, and the bus may work at one voltage while violating another device’s limits.

Before debugging software, inspect every board and module in the chain. Record which pull-ups are installed, which voltage they connect to, and whether they can be removed or switched.

Level shifting changes the topology

An I2C level shifter is not just a pair of voltage dividers. Bidirectional open-drain translation depends on the device topology, pull-up placement, edge rate, and bus capacitance on both sides. Put the pull-ups at the correct voltage domains and check whether the shifter adds leakage or delay.

The voltage-divider calculator at ResiCalc is useful for understanding why a resistor divider is not a drop-in replacement for a bidirectional open-drain level shifter. The correct network depends on the electrical behavior of the interface.

Layout still matters at modest speed

Keep SDA and SCL away from high di/dt switch nodes and motor traces. Provide a continuous reference path and avoid long stubs. If the bus leaves the board, consider connector pin assignment, ground adjacency, cable shielding, and transient protection.

For a dense mixed-signal board, MOZPCB’s controlled-impedance PCB guidance is a useful reminder that trace geometry and return paths affect signal behavior even when the bus clock is not especially fast. The goal is not to force every I2C route into a high-speed design rule; it is to keep the physical path predictable.

A practical bench sequence

1. Start with one controller and one target on the shortest connection.
2. Capture the rising and falling edges at the target pins.
3. Add modules and check the total pull-up resistance after each step.
4. Increase cable length and repeat at minimum and maximum supply voltage.
5. Test clock stretching, repeated starts, bus recovery, and power-up sequencing.

If the bus fails only when another subsystem turns on, inspect shared ground impedance and supply noise. A ceramic-capacitor selection guide can help when choosing local bypass parts for the controller, sensor, or level shifter.

Octatronics’ technical resources provide useful application context for sensor, communications, and industrial designs. I2C reliability comes from treating the “two simple wires” as a complete analog and digital system.