I had overlooked a little detail in my initial system analysis.

Even though the input frequency can reach 40MHz (due to the internal 25ns cycle time), the maximum possible output frequency is 40/2=20MHz, which could be better.

It is not possible to go higher with this circuit. However, with 2 parallel circuit, there must be a way... One ALU is read during the input clock low phase, the other is read during the high phase.

Mathematically it's not a problem because the system is highly linear. Since one accumulator increases its value by N at each cycle, it should advance by 2N after 2 cycles. Now if there are 2 separate accumulators, both advance by 2N. The system could be extended to even more phases (powers of 2 work best) if needed.

How would it work ?

• Accumulator A is reset to 0
• Accumulator B is reset to the advance value N
• Both advance with the value 2N (N is shifted left by 1 position, MSB is ignored, LSB is 0)

I'm sure I'm reinventing the wheel but... it's fun and doesn't cost me much. The only critical thing is to keep the accumulators in synch so they must be loaded simultaneously. Manual changes will require the push of a button (to load the A and B registers), until I automate this.

Assuming the input clock's duty cycle is 50%, A's MSB is output on the low phase and B's MSB is output on the next high phase. The output jitter would be only 12ns now :-)

I'm sure the performance, speed, consumption etc. would be much better with a FPGA (Most FPGA even have a configurable PLL) but it would be cheating :-D