FPGA Boot Camp #4: State Machines

If you start doing serious work, you probably won't want to use EDA Playground for everything. You can use commercial tools, which makes sense if you are targeting a specific FPGA. Some vendors have their own simulation tools and others use ModelSim or another commercial product. However, you can always use Icarus, which is open source and does a great job of simulation. In fact, that's the tool we usually pick when using EDA Playground, so even if you aren't using Icarus directly, you are probably using it through EDA Playground.

In the instructions, I offer some tips on how to use gtkwave to view the results of your simulation and give state values meaningful names as well as save your setup for future use. However, another issue with using Icarus and GTK is the size of the VCD files from meaningful simulations.

The problem is the VCD file is ASCII and not very terse. However, if your waveform viewer supports better formats (gtkwave does) you can dump your waves in LXT2 format or fst. LXT2 and fst are fast binary formats. 

To use these you probably want to change the $dumpfile directive in your test bench to use a .lxt or .fst extension. Then you can pass -lxt2 or -fst to the vpp command when you run your simulation. Then you can open that much smaller file much faster using gtkwave or any other tool that supports those formats.

When you are running simulations in Verilog, you might notice that many of the files will have a directive like this:

`timescale 1s/1ms

This tells the Verilog simulator how to mark time. What the line above means is that you want to express delays in seconds and the simulator should keep track of time down to 1 millisecond. You have to use a "decade" number for the first number. So 1, 10, or 100. You can't use 20 or 1000 or 0.5. But you can use different units. For example, instead of saying .1 seconds (which is illegal) I could say 100ms.

Suppose you have this code in y our simulation:
 

#10 reset=1'b1;

If the timescale above was in force, the simulator will multiply 10 by 1 second so that delay is a 10 second delay. It will also track the time down to 1 millisecond, although that's not important in that case. However, I can also specify delays that are fractional:

`timescale 1ms/10us
#0.333 reset=1'b1;

In this case, the computed delay is 333uS but since the precision is only 10uS, the simulator will treat it as 330uS.

The truth of it is, you don't have to have a timescale if you don't mind doing your own math. But it does make it easier to have a meaningful timescale, set your clocks to the right frequency, and then have proper time readouts in your waveform viewer.

You can see an example of this in the final project for this bootcamp. 

• Combinatorial Logic - Logic that does not rely on the previous state of the system to set the current output state.
• FSM - Finite State Machine; the formal name for the state machines we are discussing.
• Mealy Machine - A state machine where the outputs can rely to some extent on the inputs.
• Moore Machine - A state machine where the outputs rely only on the current state.
• Sequential Logic - Logic that typically uses flip flops and the current output state influences future output states.
• State - The current operating mode of a state machine. For example, a state machine may go from IDLE to ARMED to TRIGGERED. These three things (IDLE, ARMED, and TRIGGERED) are the states.
• Transition - The change of a state machine from one state to another state. It is possible to have a machine state that transitions to itself.

You probably use a variety of state machines every day. Some of them may be in FPGAs, some in software, and some might even use old-fashioned regular hardware. Here's some common examples:

• Traffic lights
• Cryptography machines
• Vending machines
• Gas pumps
• Video recorders

Can you think of other examples?