RISCV SoftCPU for 2018 Contest

It was crashing yesterday, I forgot that my address decoder had a wrap around issue, after fixing that Zephyr RTOS Philosophers example runs!

Pretty cool. Demo is available for download now

https://github.com/micro-FPGA/engine-V/tree/master/boards/lattice/iCE40-UltraPlus-MDP/demos/zephyr

Source will be revealed a bit later :)

The trick to compile the dhrystone properly without chaning the dhrystone code was to append LL to HZ definiation in utils.c

This is correct output to be expected from the dhrystone test, please note that the "mcycle=.." should also come unless you have changed the syscalls.c from riscv benchmark github too much!

There are simulators available but the best way to have all tuned up and tested for the SoftCPU is to write own simulator first.

This is pretty simple task, spent maybe 11 hours to get the simulator to pass all RV32I compliance test cases all test except those that use CSRs or traps are working. Verification with the original compliance test suite signatures.

Next step with simulator is to pump it up to run, hello, then dhrystone and then boot zephyr (a requirement by the contest rules)