VHDL library for gate-level verification

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Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries

yann-guidon-ygdes

Yann Guidon / YGDES

1

Get and install GHDL

get it there : https://github.com/ghdl/ghdl/releases

also read http://ghdl.free.fr/

Be sure to not use the MCODE version... The GCC and LLVM backends seem to work well.

2

Test

under Linux :

wget https://cdn.hackaday.io/files/1625946956421696/A3Ptiles_v2.6_20191229.tgz
tar xzvf A3Ptiles_v2.6_20191229.tgz
cd A3Pv2.6
./run_tests.sh

This will run scripts for a minute or so, compiling everything and testing the results for consistency.

3

Use in your project

Copy (or symlink) the directory proasic3v2 in your project.
Use the tests/examples to setup your scripts and include the proper paths to the files.

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