Lion FPGA CPU/Computer

Added a vector graphics controller in the fpga with 4K dedicated ram for 1024 vector end points.

Now it uses 3x MPC4822 12bit dacs for all channels.

It produces the x,y,z output signals that I feed in my recently acquired HP-1330A X-Y Display Monitor.

I implemented the Bresenham's line algorithm in the fpga to draw a line from the previous drawn point to the last one.

I converted the Astro java demo game for vector graphics!

Raster and Vector graphics are totally independent and can display concurrently.

The following picture was taken before implementing the line draw algorithm:

And the next photo is with the line algorithm, unfortunately with my phone camera lines look fat, in reality they look much better:

Sound capabilities are not advanced in Lion but...

I increased the sound channels to 3 and added 255 step 8bit digital volume control for each one.

A channel outputs a square wave signal with frequency  obtained by dividing 200khz by a 13bit number.

A channel can be mixed with the white noise (lfsr) channel, noise comes with a frequency bandwidth limit.

Every channel can be enabled with 8 different duration values 2sec, 1sec, 0.5 sec,  ....

Status of any channel is available to determine if it has finished playing the previous note in order to send it a new note but a channel can be interrupted any time to start a new note.

Moved the project to Cyclone V FPGA 5CEFA2F23I7, now I don't use an external static ram chip because this FPGA has enough internal ram for Lion's 128K ram + 32K Video ram + 12K sprite ram. It also has plenty IO pins for new features and it's logic elements are faster.

At last I wrote a controller for PS/2 keyboard in the fpga. It has a 16 key queue.

I was postponing it and was using an external board instead, but once I started, it was easy and fun.

I keep adding instructions that i think are useful or add speed as long as unused opcodes are available.

I added ram block transfer commands. The IDX register that was used as a loop counter and index, is used by the transfer instructions to hold the number of words to be moved.
Instructions MTOM, MTOI, ITOM, ITOI with two arguments An1,An2 move fast blocks of words starting from memory or IO address An2 to memory or IO address An1.

Instructions NTOM, NTOI with arguments An1,N or An1,An2 fill the block pointed by An1 of size IDX+1 with the 16 bit value N (or An2).

    MOV A1,buffer1
    MOV A2,buffer2
    SETX 99
    MTOM A1,A2  ;copy the 100 words block starting at buffer2 to buffer1
    SETX 99
    NTOM A2,0   ;fill buffer2 with zeros

These new instructions drastically improved scrolling routines speed

When I first started to design the cpu I thought that 16bit address bus is ok for a homebrew cpu but after I made the Lion computer 64K rom+ram seemed very small although it used separate video and sprites ram. I wanted more memory and the more convenient way to do it is using pages. So I added 3 more address pins to lion cpu and added the necessary commands to support 8x64K pages.

The SR register was extended from 8 to 16 bits and now the 9 most significant bits bit15 to bit7 hold the current code (bit15-bit13), data (bit12-bit10) and stack page (bit9-bit7).

Instruction SDP sets the current data page, SSP sets the current stack page

PJMP jumps to another address/code page.  PJSR jumps to a subroutine to another address/page and PRET returns.

Also another register named OtherDataPage ODP assists in data transfers between pages by holding a source or target page for use with instructions PMOV PMOV.B

Interrupt routines always use page 0 as a code page.

I'm currently testing the functionality of this implementation and need to make more changes to the assembler

Fixed some issues with the keyboard, now Shift and Caps Lock work well, although I cannot turn the Caps led on due to the external controller board I use limitations. Maybe I have to build my own as i did with everything else although I find it not so interesting.

Since I made a second video mode for graphics and added more vram I used the extra ram to also upgrade the first video mode for text so its now 640x240 pixels and with a 8x8 font can display 30x80 characters in two colors per character from 16 available.

Added a second parallel sprite engine so now 28 sprites are available for mode 1 in 8k sprite ram. It is synchronized using the vertical synch signal with the video controller that generates the first 14 sprites. Sprite ram is now split in two 4k independently addressed units so each sprite controller has its own ram. Sprite ram is mapped in I/O space at address 16384.

I can any time easily add one or two more sprite controllers to have 42 or 56 sprites.

Number of mode 1 sprites increased from 10 to 16.