A small design created with GreenPAK designer for SLG46110 is now working in 3 different FPGA's Xilinx Spartan-7 (S7-mini from BML), on Lattice XO2-4000 and in GOWIN 1NR9 FPGA. Bitstream loading over simple UART ASCII download protocol.
This is the circuit I am using for testing, the clock is selected 25KHz and pre divided, so the output is visible blinking, sending "AT" in Morse code.
You created VHDL library of components compatible with GreenPAK, right? Does GreenPAK designer generates VHDL from this circuit and then you synthesize it in any other VHDL tool? Or you reverse-engineered their bitstream and you can run it anywhere?...
You created VHDL library of components compatible with GreenPAK, right? Does GreenPAK designer generates VHDL from this circuit and then you synthesize it in any other VHDL tool? Or you reverse-engineered their bitstream and you can run it anywhere?...