[Edit: I've added a schematic for this circuit at the bottom of the log!]

I'm not sure what exactly I was thinking of when I wrote the previous log about handing the /BOOT line, but it's completely and utterly wrong. Luckily, I realised this when actually designing it properly (rather than just hacking around in Logisim).

The short version is that, in the log, I said I needed to hold the /BOOT line low for the first four clock cycles - this is wrong in a very important way: it's not four clock cycles, but four memory cycles!

Once I'd realised it was wrong, I went back to the 68000 users manual to check the timings for those initial reads. I also hooked up the logic analyzer to the 68010 to make myself absolutely certain that the chip would actually do the four 16-bit reads I expected after /HALT and /RESET are deasserted. I wanted to double-check this because if it did eight 8-bit reads I'd have to redesign the address decoder to support /UDS and /LDS when /BOOT was asserted.

Thankfully, it looks like it does exactly what I expected (I've annotated the screenshot for clarity):

You'll notice it's actually 16 clock cycles for the four reads (assuming zero wait states). However, this doesn't actually matter - because I know it's four memory cycles, I can simply drive the shift register with the /AS line instead of CLK. Once there have been four cycles, /BOOT will be deasserted and all will be right with the world.

Also, as mentioned in the screenshot, because the initial SSP and PC are fetched with 16-bit reads, I don't need to worry about /UDS and /LDS when /BOOT is low.

So yeah, dodged a bit of a bullet there...

Update: Here is the schematic for the actual circuit that handles the /BOOT line:

And how it looks when analyzed (The important lines here are /AS and /BOOT, the other Qs are the outputs of the intermediate flip-flops I was looking at while debugging a mis-wired connection):