Time to use this in my own projects now! 
Just added it to my WIP Smart Home board, and it seems to fit well so far :> 

The eight pins work great for the ESP's UART, I might even have enough free to squeeze JTAG alongside it.

Thanks <3

Great! Let me know if you can think of any way to improve it. 

I love this idea and am planning on using it on a project soon. I have a question about the thin traces used to escape the NPTH. What trace width have you had success with? I am planning on using the SOICbite to program an ATtiny85. Thanks for creating this!

Hi Sam, I have used 0.17mm traces to escape the centre pads "as-is". However, if you open the part in the footprint editor you can change the pad clearance for the holes to something smaller. This should let you use wider traces. I may need to do a design revision to make this standard. 

I'm not sure I understand what you mean regarding the pad clearance. I am running into an issue because JLCPCB says that their minimum NPTH to Track clearance is 0.25mm. My EDA seems to think that with .17mm traces, there is a clearance of around 0.195m.

@SamGurdus1 if you open the SOICbite footprint in the kicad footprint editor (or whatever your EDA equivalent is) and go into the clearances on the NPTHs (select one NPTH and press "e" in kicad, then I think it's the third tab along in the pad edit window).

I've used 0.17mm on several boards with SOICbite from JLCPCB and haven't had any issues with that design rule. 

Thank you so much for this! I used the SOICbite on my latest project (https://hackaday.io/project/170302-12-switches-1-led-1-sao) and it made programming (and reprogramming, and re-reprogramming) a breeze! I'll definitely use it for future projects as well!

Hi @Sam Ettinger thanks for taking the time to try this and let me know how it helped you - made me smile! I love your project. Just wish the "S" in SAO stood for something else! 

This is so much better than that Tag-Connect garbage. multi-source, inexpensive, configurable... great job!

Thanks @akohlsmith . It's not perfect but it has a lot going for it. Please contribute to the github repository if you do any mods or breakouts with it. Even verifying the layout drawing would be useful!

FYI I successfully used the Eagle footprint on my newest board. Works great but the clip I used needed more than a bit of modification to work properly and probably needs a stiffer spring.

All told it's lived up to it's promise! Great job

@siddacious I'm so pleased and it's great that you took the time to let me know it helped you. Thanks. I have noticed a stiffer spring would be better but that it often improves if you go back and cut out a bit further/cleaner into the hinge section. Most of the resistance to closing on my three clips (I don't take them off the programmers now!) is usually a sliver of plastic that hasn't been cleanly cut away in the hinge area.

Very clever. I just bought two clips to try it out.

Do you have a PDF/Image with a dimensions for the recommended holes and pad sizes and spacing (looks to be on a 25mil grid), as I don't use either Kicad or Eagle. If not I'll install Kicad and then look at your footprint, but a document would be helpful for future reference.

@Peter Elliot I do need to provide a drawing. Will try tomorrow. However, do note that it will only be "what works for me" rather than anything canonical. 

@Peter Elliot I have added a drawing - let me know if it's missing something you need. All units mm.

Thank you. I'll try it out and let you know how I got on.

Where did you purchase your SOIC clip?  I purchased this one on Amazon:

https://www.amazon.com/Ximimark-SOIC8-Socket-Adpter-Programmer/dp/B07BRSVRXV/ref=sr_1_5?keywords=soic+test+clip&qid=1561491531&s=gateway&sr=8-5

But the clip doesn't clamp down far enough to actually grab onto a normal circuit board.

You have to modify the clip. Shave down the plastic that keeps it from closing further until it closes far enough.

Thanks, don't know how I missed that the first time I read through this.

Does the clip register before it makes contact?  IOW, can the clip contacts short two pads while you are connecting the clip? (I don't have a SOIC test clip so I can't measure or experiment.)   The TagConnect registers before making contact.  Wouldn't be a problem if board and clip are unpowered, but something to think about.  Since I only need four pins, I could separate the pads more, rip out every other contact on the clip.

Clip spring contacts do touch the PCB pads before the claws/teeth resister (or not) so it's possible that you could short the pads together. If the pad space were greater than the clip contacts, you'd find this much less of a risk. Most SOIC clip assemblies seem to have a cable with an IDC connector on the other end, so I just disconnect that, attach the clip and then attach the IDC connection.

You  absolutely could make your pads sparse and customise your clip. I would recommend against having VCC and GND on "diagonally opposite" pads (e.g. 1 and 5 or 4 and 8) so you can't reverse power the board if you get the clip on the wrong way round. I think this is unlikely because the ribbon cables attached to SOIC clips usually have an index wire of a different colour (e.g. red instead of grey) which you can use as Pin 1, lined up with the Pad 1 of the footprint (denoted by the silkscreen partial outline round the pad).

Also, I see that the contacts don't mate while the clip is not attached.  Which is good.  But one must be careful not to hack the clip so much that they do.  Then one might need to be more careful about connecting:  connect to board, then connect to programmer, as you have already stated you do.  In my case (4 pins), I want to put Vcc opposite ground (so as you say, they are not diagonal) but if they do mate, and are plugged into the probe, they would short the probe power supply.  Stuff to think about.

Clever, nice work.  I use TagConnect, this seems better.  For SBW (SpiByWire), you only need two pads on each side.  I wanted to hack at my TagConnect, now I will do this instead.

Thanks, looking forward to seeing the results. 

Great idea, thanks!

Seems like the holes wouldn't need to be NPTH, if that removes a PCB build step and mfg cost.  Just make the pads the same size as or about 0.002" larger than the holes.

Keying:  could leave out some holes or use additional key holes or slots (with longer pegs added) to either side.  Board edge notches perhaps, making the connector easier to find.

Good thoughts, and thanks for thanking! Although, I'm not sure I understand you correctly. The holes are staggered, relative to the pads, so I don't know if your suggestion would work how you imagine. As I said, I may have missed what you mean though! Also, this is two sided, so a PTH would possibly connect two different signals together. I haven't found NPTH to be an added cost on the board houses I use but if you'd like to submit a version with your changes to the Github repo, I'll host it with the others.

Ref keying, since publishing this I do wonder whether an edge-notch would be a good way to quickly line up, just as you have. I think it would require more modification to the clip, so I haven't done anything with it for now. Willing to take EDA footprint files as suggestions though!

Clever... I wish I had done this rather than hacking my own pogo connector which I then had to try to hold in place manually. Your solution is cheap and ready to use and requires no special fixturing. Love it!

Thanks - wish I'd followed up on the concept sooner as all my boards are going to have one on now.

Great idea! What do you think about recommending a standard pin assignment for this interface? (GND, Vcc, TX, RX, SCK, MiSo, MoSi...) This might become a "de facto standard"!

...reset)! Yes, I have no objection to this but in it's current form with the end four pads being easiest to escape I wanted to leave people the flexibility to define their own assignment. I would be happy for a standard to develop as long as it was clearly marked as a standardised version - this truly isn't for me to decide though and I'd be happy to add project team members who'd like to work on this aspect.

I know of at least one engineer who is interested in e.g. SWD and more than one ground pad. His "ideal" would require 10 pads but the next size up SOIC test clip that I'm aware of is 14 pins, so we'd need to cut one of those down. They also don't appear to be available as cheaply as the SOIC 8 format, understandably.

Contributors and team members welcome!

IMHO this is absolutely cool (and scaleable! ). If you just need to flash your code on your product, requiring e.g. power, SWDIO and CLK, on a bunch of boards, this approach will save a lot of space, time and funds.
If you should need  more functionality in R&D, go for a complete JTAG header. Size should not matter that much then.

@imalipusram thanks, hope it helps.

That is just ingenious!!! 

BTW why do you need vias (NPTH)?

Well it's just a way to mechanically align and retain the spring contact with the pads. There are teeth/claws on the SOIC clip that engage with these NPTH to align the clip with the footprint and hold it in place.  If you wanted to remove them, that would be fine. I have been pondering removing the middle three holes and seeing if the outer two could achieve the same function - this would require another physical modification to the SOIC test clip, as you would need to cut or abrade down the top and bottom middle three (six total) "claws", leaving just the outer ones to engage. One benefit of removing the middle three NPTH would be easier escaping of traces. Feel free to push a new version on the Github!

If you make the pattern asymmetrical (e.g., omit just the 3rd and 4th out of 5 NPTHs), you've now got a keyed connector

@jepler that's a nice idea. If you look in the side profile of the SOIC clip I modified in the project photos, you'll see that the spring conductors of the clip are closer to the PCB, so I don't think this keyed design would save you from VCC touching the wrong pads but visually it might help you line stuff up. 

FWIW, I unplug my IDC connector on the other end of the ribbon cable, then connect the SOICbite and then replug the IDC in. Only takes a second but makes me feel better!

That's really clever.

Thank you for sharing.

You're welcome!