Super excited to get a little box from JLCPCB. To find the next version of The Basic-MC6800 V1b.
Really loving how the boards are starting to look. Black was really the way to go.
The finish is nice and clear as well. Really looking forward to getting the other parts for this and building them up.
Over the last few months I have been putting some time into researching the MC6809. The processor is quite well known and is used in most of the Tandy TRS-80 colour computer range (The COCO). which Incidentally has led me to spend lots of time listening to the COCO Talk Podcast. I have also found out that the Hitachi 6309 would also be a good fit for this board with faster clock rates and low power overheads. could be something to experiment with later.
So at the moment I'm just waiting to get some parts to build 1 or 2 of these and see if i can execute some code :)
Thought it may be time for a brief update as I have been quiet on this for a while.
The Basic-MC6800 is still an active project it has just been n the back burner for a little while while i have been working on other things.
I have pretty much completed the next version of the board. It is now waiting to be sent off the JLCPCB.
I have made some updates to the control logic using a set of and and or gates so now the control logic should work. I have also broken out a few spare inverters just in in case they are needed for modding later. I have added a series of mounting holes so I can add future boards on the front. The other thing to not is i Changed the crystal package over the a HC49 landing as these are more freely available in for crystals < 4MHz.
Looks the part in the 3d render.
Still wondering if the skinny DIP is the right choice for the RAM.
This project slowed after the Retro computer fair i was going to take it to was closed down but ii'm getting a feeling for continuing this project further.
I managed to build one of the REV1 boards and have been spending some time on an off working out all the kinks before going to the next version.
i decided not to puth the decade counter on for the moment though that will be something i will come back too.
I also found some issues when it came down to the pulling of certain pins.
Out of habit i had already added pull-up resistors to the interrupt pins to try and keep them stable aslos the same situation with the reset pin.
Soon after I found out that the reset pin has no internal pull-up resistor either so that is the reason for the resistor that can be seen in the above image.
The other issue was the when the device was free running it would swap between different speeds. A0 was jumping between pulsing at 100KHz and 10kHz and when i touched the back of the board in a certain way it would stabilize.
After a little further investigation I discovered the DMA request pin didn't like being left floating as it would issue a dma request which cause the Processor to release the address and data bus for up to 16 cycles.
The final fault that i am still trying to thrash out before moving forward is running from a xtal so far the only way i have had the chip running is a buy using an arduino to generate the clock signal.
As you can see in the above video the processor is free-running and showing the output form A15 and A13. which give a 1:4 flash pattern. It easy to also see where the clock signal is patched in.
Last thing to check is can it execute instructions from ROM and can it store values in RAM once these are tested I can move forward with REV2
I always feels nice to receive a PCB you have designed.
Even though I know that there is a problem with the ROM and peripheral selector on this board i feels good in the had and should give me enough to work with at least to see it running.
Really pleased with how the silk looks, by the way the bin is ASCII (nerdy i know) :)
another nice arrival was the Processors themselves surprised about the date code week 22 2018 so reasonably new chips looking in great and unused condition. I am hopeful for these i need something to set the free running though.
After my mistake with bridging the outputs of a 3 to 8 decoder I have been taking another look at the address logic. I believe that I can use OR and NOT gates to do the selection between the ROM RAM and peripherals. I have come up with this. I still have to check it with a logicsim but seems it sane. the nice thing is I can use some of the spare NOT gates for the Q and A15 inverters so extra bonus.
As pointed out here and on twitter I have my decode logic for the ROM and Peripheral addressing a but wrong.
well blue magic smoke kind of wrong :D
this circuit
would mean that if any of Y7 to Y1 are active then it would sink the the current from the rest. The high state of each gate is provided by a 120ohm resistor this means, 6 x 40mA would sink into the active gate.
There is not really a way to bodge this well so on this pin of the board i am going to hardware _A15 to ROM _CS or maybe do something else of board.
I'm experimenting with ideas but i think my final solution will look something like this.
using multiple OR gates to drive the select line. I this format I think the select will be low only if every input is off. this is taken from the IO board I am currently working on.
Finished the initial design the 64K address space is divided up as so.
0x0000-0x7FFF RAM
0x8000-0x8FFF Peripheral space
0x9000-0xFFFF ROM
I initially had the ROM at the bottom of the address space and the RAM at the to how every thanks to many people on twitter I was informed that the Reset Vector this is a memory address that contains the first address to execute code from should be contained in ROM (this is something I didn't know before this project). The Reset Vector for this MPU is 0xFFFE right at the top of the address space so the RAM and ROM got swapped.
I decided to use a 3 to 8 decoded to select the peripheral instead of basic gates The reason is if i want to add a display buffer or other device i could take a lead form that sacrificing 4K of ROM space.
_A15 is the inverse to A15 generated by a FET and pull-up resistor so it goes low when A15 is high. I also needed it to select between this and the RAM at the bottom of the address space.
This the full schematic have been over it several times and believe cleaned up any issues.
This is board almost as it has been sent off to the board house I did some more trace optimizing and managed to remove a load of vias.
As you see in the area I have marked in blue.
So now the PCBs are ordered with JLCPCB so just a waiting game.
Gee Bartlett
