The core of the board is much the same as the other 6800 style boards. A 74HC573 (U2) is used to latch and demultiplex the bus from the processor (U1). The motorola style E clock and RW line is converted into Z80 style R/W lines by three nand gates (U4B-U4D). A 74HCT688 matches a 256 byte address range and drives IORQ accordingly. U4A in turn inverts that to generate MREQ. Whilst the Z80 drives MREQ and IORQ as needed the fact we qualify RD and WR with the E clock means that there is no confusion. M1 is pulled high as we don't support Z80 style IM2, and that ensures that IORQ with neither RD or WR cannot be misinterpreted.

The board provides the 7.3728MHz RC2014 standard clock and the RC2014 clock rate happens to be perfect for up to 115,200 baud whilst staying under the 8MHz limit on the CPU.

A MAX811 is used to provide a clean reset to the processor (which for a 68HC11 is important), and the 4K7 resistor (R4) protects it against other things driving the line low.

The built in serial port is protected by 1K resistors and made available on the edge of the card, along with port E and the SPI plus some GPIO as chip selects.

Jumpers permit the serial line to be connected to the backplane, and also the E and RW signals to be connected to user pins as the 6502 and 6303 cards do so that they can be used by 65xx/68xx peripheral chips.

PA6-PA3 (OC2-OC5) are routed so that an 80pin connector can be used (with just four pins on the extended bus for A16-A19) to drive a linear memory card. This has not yet been tested.
The final oddity is JP5 which allows the external I/O window to be placed at $7Exx or $FExx. The latter is generally more useful but if running things that expect only ROM at $E000-$FFFF then the I/O can be moved lower in the map.

In theory it should be possible to run with a 68HC11E9 containing the Buffalo monitor ROM and no RAM/ROM card just using the internal RAM. For other use cases you need ROM in the top of memory space. The 32K/32K card can do this and the 512K/512K banked memory card likewise.