LED Coupled Logic (LCL)

Project Logs

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Current Mode Logic with Transistor/Diode Pairs
Tim • 02/24/2021 at 07:09 • 0 comments

Found in the Motorola High Speed Switching Transistor Handbook from 1963. Looks like LCL was pre-anticipated by implementations with germanium transistors and diodes.

The book is extremely interesting - the best book on discrete bipolar logic I have seen so far. It goes way down into theory and device physics:

https://archive.org/details/High-speedSwitchingHandbook

RINGO9 Characterization

Tim • 12/12/2020 at 13:56 • 0 comments

I used 9 inverters from two RINGO5 boards to build a single ring oscillator with 9 stages. Due to the lower oscillating frequency, the individual inverters are able to reach a more steady state during switching.

Vdd [V]	Idd [mA]	Vavg [V]	Vmin [V]	Vmax [V]	Swing [V]	Freq [MHz]	tpd [ns]
4.5	80	3.36	2.86	3.83	0.97	70.7	0.78
5	92	3.81	3.01	4.54	1.53	58.6	0.94

The tpd and logic levels are very similar for the RINGO5 and RINGO9 confirming sub 1ns tpd for the LCL inverter.

RINGO5 Characterization

Tim • 12/12/2020 at 12:59 • 0 comments

The assembled PCBs arrived after just 11 days. This is a short summary of the circuit characterization.

The full circuit of the five stage ring oscillator is shown above. I used MMTBH10 HF-Transistors in the actual built instead of the MMBT3904 that are shown in the circuit diagram. Since the source follow provides a low impedance output, I did not add an additional output driver and attached the scope directly to the output of the rightmost inverter.

The two trace above show the ring oscillator at VDD=2.7V, the minimum voltage where it oscillates and at 5V.

Vdd [V]	Idd [mA]	Vavg [V]	Vmin [V]	Vmax [V]	Swing [V]	Freq [MHz]	tpd [ns]
2.7	18	1.81	1.68	1.95	0.27	222	0.45
3	22	2.08	1.92	2.25	0.33	213	0.46
3.5	28	2.57	2.41	2.72	0.31	176	0.56
4	35	2.96	2.65	3.25	0.6	144	0.69
4.5	42	3.38	2.9	3.85	0.95	115	0.86
5	47	3.82	3.08	4.54	1.46	100	1

Detailed measuremt results are shown in the table above. A minimum of 2.7V is needed for the oscillator to start oscillating. This seems to be governed by the forward voltage of the (red) LEDs. At this supply voltage there is very little voltage swing at the summing node of the differential pair, meaning that the inverter essentially works as a common emitter amplifier. At 450 ps, the extracted tdp is quite low, but it's arguable wether we are seeing digital switching. The output looks like a clean sine. One issue may be that the impedance of the scope probe is too low at the harmonics and is remove any edges. I need to look into an impedance matched set up.

Going to higher frequencies we see an increase in output voltage swing, but a reduction of frequency. At 5V the tpd is still at a respectable 1000 ps.

PCB
Tim • 12/01/2020 at 22:42 • 0 comments

Should arrive in a couple of weeks, fully assembled.
LED Coupled Logic
Tim • 11/30/2020 at 22:48 • 0 comments

I'll try to keep it brief. You have seen me investigate several different styles of discrete logic, including the weird DTL derivative LTL.

One obvious omission was emitter coupled logic, ECL.

A basic ECL inverter is shown above. The key is the long-tailed pair on the left side, which acts as a saturating differential amplifier. The emitter follower formed by Q4 is used as a voltage buffer and sets proper input logic levels. The non-input branch of the input pair is typically tied to a reference voltages which is in-between logic low and high levels. Since ECL does not drive the transitors in saturation, it can be extremely fast. Due to high static biasing it is also extremely power hungry, roughly 10 mA per gate. The Cray 1, one of the most famous supercomputers was entirely based on integrated ECL logic.

Let's ponder about the right side of the differential pair (Q3). It does not only consist of a resistor and transistor, we need a static bias reference in addition. This adds a lot of components to what could be a simple RTL or NMOS inverter.

But who says we have to form a differential pair from two identical transistors? The circuit above shows an inverter formed from an assymmetric differential pair consisting of a LED and a bipolar transitor. The benefit of this is that it saves one transitor, one resistor and the bias reference.

The plot above shows the input-output relationship of the inverter. The threshold level is at 3.0V, the high level is at 3.25V, while the low level is at 2.8V. The output voltages increases again if the input is driven far above Vh. This behavior is similar to ECL.

To test the propagation delay, I simulated a simple 5 stage ring oscillator.

Oscillator frequency is 138.7 MHz, which means that the tpd is 720ps. There is some overshoot, which appears to increase voltage swing.

Just like for ECL and RTL, the basic gate for this logic style is a NOR gate. The output buffer allows combing the outputs of several gates to form a wired AND.

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Discussions

Yann Guidon / YGDES wrote 12/12/2020 at 23:51

Thinking out loud :

The diode's drop is about 3 to 4 times the Vbe. What if it was 2×Vbe ? There would be less saturation in the output transistor's ... Oh but it is not saturated because it's a common emitter and having only 1× Vbe of output swing wouldn't help, I guess... so Vdrop should be around 2V or 3×Vbe, or 3× silicon diodes.

I suppose an old red LED would be great.

Did you measure your diodes' drop ? or even probed that node ?

Are you sure? yes | no

Tim wrote 12/13/2020 at 08:53

Yes, I probed that node. At low VDD it will remain constant, so that the inverter actually only acts as a common emitter amplifier. This is where you see the low swing very fast switching. At higher VDD the differntial node also changes (LED capacitance has to be charged), leading to high logic level swing at the cost of speed.

There is of course the issue of voltage variation introduced by the VF variation of the LEDs. This would be reduced with a proper voltage reference like in ECL.

The inverter works with both green and red LEDs. For green LEDs I need to raise VDD to ~6V, red are default.

Are you sure? yes | no

Yann Guidon / YGDES wrote 12/13/2020 at 10:58

You made me think of another idea !

Instead of having the diode in parallel with the input transistor, why not having it in parallel with the "common" low-side resistor ?

This could stabilise the logic levels precisely, independently from the resistor values, adding a pretty strong non linear behaviour at very low cost.

I'll have to simulate that...

Edit :

It was a stupid idea that doesn't work :-D

Edit 2 :

Daaamnit it works MUCH better when you wire the diode in the right direction !!! I should publish somewhere :-D

Click https://tinyurl.com/y4kwm7v4 for a preview :-)

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Tim wrote 12/14/2020 at 08:06

>Instead of having the diode in parallel with the input transistor,

This is basically fixing the emitter potential, turning the inverter into a common emitter amplifier, or an RTL gate. Of course it will still amplify :)

At lower voltages the LCL gate is actually operating in the same mode. It's in the dark grey area between actual logic and an analog circuit...

But who says this cannot be used for logic in some way?

The benefit of the tail-resistor in the ECL/LCL gate is that it will move the emitter potential up if there is too much collector current. This can prevent saturation, if biased correctly. If you short the emitter resistor with the diode, you will drive the transistors into saturation the same way it happens with RTL.

Are you sure? yes | no

Yann Guidon / YGDES wrote 12/12/2020 at 20:31

What if you reduced the resistor's values ? The high side seems ok but 100 ohms on the low side would probably increase the speed/power ratio, I suppose ?

Are you sure? yes | no

Tim wrote 12/13/2020 at 08:49

Since this is non-saturating logic, changing the resistor values is a bit tricky. The ratio of R1 to R2 basically defines the logic levels in connection with the supply and forward voltages of the semiconductors. The biggest lever on speed is actually to change the logic levels to minimize swing. But of course that comes with noise margin issues.

Are you sure? yes | no

Yann Guidon / YGDES wrote 12/13/2020 at 10:53

I see, because a limiting factor is the RC constant of the output for example...

Are you sure? yes | no

Yann Guidon / YGDES wrote 12/01/2020 at 18:03

I should try this with my AF240s (Ge) and those ultrafast BFS480 :-P
one day.

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Yann Guidon / YGDES wrote 12/01/2020 at 17:30

Note : this trick only works if you only desire the NOR gate. ECL is great because the complementary output is also provided, it greatly helps to have both outputs for logic minimisation and saves another inverting layer.

Are you sure? yes | no

Tim wrote 12/01/2020 at 19:20

Well you could mix the gates with true ECL gates if you need a complementary signal.

Are you sure? yes | no

Yann Guidon / YGDES wrote 12/01/2020 at 20:02

yes, the saving is significant. But then you need to tune your ref with the diode drop, and/or vice versa

what an interesting challenge ;-)

Are you sure? yes | no

Yann Guidon / YGDES wrote 12/01/2020 at 17:24

I suspect 2 things :

* The LED can be replaced by a couple of Si diodes for example

* The capacitance of the PN junction is a bonus and not a drawback

Are you sure? yes | no

Tim wrote 12/01/2020 at 19:25

The differential junction has to move relative to VDD, so the capacitance should play some role. I made some trials attaching parasitic caps to various nodes and was quite surprised that there was little effect. The output impedance of the gates is really low, due to the emitter follower. This helps quite a bit.

A true ECL gate is still a bit faster, but that is also because the additional gm of the reference side helps a bit.

Yeah, Si diodes should also work in place of the LEDs.

Are you sure? yes | no

Yann Guidon / YGDES wrote 12/01/2020 at 20:03

This sounds promising :-)

Are you sure? yes | no

Yann Guidon / YGDES wrote 12/01/2020 at 17:21

OK you won the internets today :-D

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Dr. Cockroach wrote 11/30/2020 at 22:42

Looking forward to this project. For sure I expect LCL to be faster than my Light Logic :-)

Are you sure? yes | no

Tim wrote 11/30/2020 at 22:51

It is for sure. Maybe LED-coupling is a bit of a misnomer here. I am not sure whether the "E" in ECL refers to the emitter follower or the differential pair :)

Are you sure? yes | no

Yann Guidon / YGDES wrote 12/01/2020 at 17:35

ECLED ?
Emitter-Coupled LED ?

Are you sure? yes | no

Tim wrote 12/01/2020 at 19:26

ECLEDL? It needs an additional L for "logic" :)

Are you sure? yes | no

Yann Guidon / YGDES wrote 12/13/2020 at 00:45

Who cares ? :-P

Are you sure? yes | no

LED Coupled Logic (LCL)

Description

Project Logs

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Current Mode Logic with Transistor/Diode Pairs

RINGO9 Characterization

RINGO5 Characterization

PCB