Demo Video!

Premise

I heard about the 555 timer contest at the beginning of Dec 2021 and I wanted to see just how silly the 555 could be pushed. Inspired by the silliness at SIGBOVIK (especially the On The Turing Completeness Of PowerPoint project by Tom Wildenhain ), I wanted to try to answer the question "Could you make all the ingredients necessary to make a solely 555 timer (or variant) based Turing Machine?"

Early Research / Simulation / Breadboarding (Early Dec 2021 through Dec 8, 2021, give or take):
I busted out my breadboard and what TLC555s I had kicking around and looked at the datasheet to see what truth tables (and other various behaviours) could be extracted from the 555 or combinations of it. Although my implementation for this project didn't include all of my findings, I did document what other gates (I also incidentally made a boost converter with the 555's DISCHARGE pin too!) could be extracted out of a 555 along with how to construct them and their measured breadboard propagation times. All of which can be found on the project github page here: https://github.com/lambdawolflabs/555-Timer-Functional-Complete-Logic-Gates  (Specifically here: https://github.com/lambdawolflabs/555-Timer-Functional-Complete-Logic-Gates/blob/main/555_Gates_Findings_12-4_and_12-5-2021.txt )

Early Breadboard Tests Figure:

I wanted to see if I could stick as much as possible with the 555 being the sole active element, ala trying to relying upon external discrete transistors, diodes, etc (and of course no other ICs other than 555s / 556s). This led to the gates that I found / designed to be hybrid NMOS and CMOS logic. (The 555's DISCHARGE pin is just as useful as an output as the explicit OUTPUT pin!). This segment was some-what trial and error but from the breadboard I used Logi Sim's built in combinational logic solver to extract equivalent functions ( http://www.cburch.com/logisim/ ).

I learned that the Bipolar 555s are much too slow in propagation times (on the order of single digit microSecond propagation time) vs the hundreds of nanoseconds of propagation time for the CMOS 555s. This shouldn't be a surprise given CMOS has higher input impedance and lower input capacitance compared to Bipolar.

I also recreated the circuits in LTSpice to verify the logical functions and propagation times too. I only had the NE555 SPICE Models to work with, but CMOS and Bipolar 555s are functionally identical. (Full simulation directory here: https://github.com/lambdawolflabs/555-Timer-Functional-Complete-Logic-Gates/tree/main/Simulations )

From this, I decided to go with the (relatively speaking) fastest gates I had found thus far:

• Intrinsic 2 Input AND Gate (CMOS inputs, NMOS output) - Uses 1x 556 or 2x 555s
• Intrinsic 2 Input NOR Gate (CMOS inputs, NMOS output) - Uses 1x 556 or 2x 555s
• 3x NOR Based 2 input XOR Gate (CMOS inputs, NMOS output) - Uses 3x 556 or 6x 555s
• Intrinsic NOT Gate (CMOS inputs, CMOS outputs) - Dual Inverters (556) or Single Inverter (555)
• Intrinsic Safe-RS Flip Flop (CMOS inputs, CMOS outputs) - Dual Safe-RS Flip Flops (556) or Single (555)
  • Note: This is already available to the 555 so nothing amazing here.

 Schematic Capture (Dec 8 - Dec 18th 2021, give or take)

I knew going into this that there was going to be alot of repeat work, both on the Schematic side and on the PCB layout side. So that meant hierarchical schematics and replicate layouts as much as possible. After some searching, I fortunately found MitjaNemec's Replicate Layout plugin tool for KiCAD ( https://github.com/MitjaNemec/Kicad_action_plugins ) which, honestly, probably made the layout possible within the timeframe of the contest. Excellent set of tools, massive kudos to them!

Full schematic can be found here: https://github.com/lambdawolflabs/555-Timer-Functional-Complete-Logic-Gates/blob/main/Sch_RevA_555_Timer_Functional_Turing_Complete_Project.pdf

There was a lot of checking and rechecking to make sure...