BoxLambda

https://epsilon537.github.io/boxlambda/forth-and-c/

https://epsilon537.github.io/boxlambda/sw-arch-1st-draft/

https://epsilon537.github.io/boxlambda/minimizing-interrupt-latency-and-jitter/

## Label `v0.1.0`: Changes sinces label `boxlambda_simplified` - 2025-07-07

### Added

- Corsair-based register map definition and documentation.
- Software component `sdspi`.
- Enabled HW flow control support in the UART core.
- Bootloader as default IMEM image initializes SDRAM and loads application image from flash into IMEM.
- A "make sw" target to build all the software projects without building any
gateware projects.

### Fixed
- Fixed bug in Ibex Single Instruction Prefetcher related to handling of multiple
near-simultaneous interrupts.

### Changed
- Triggering code (re)generation when (re)generating build tree, or when
explicitly requested using `make cgen` command. No longer triggering code
(re)generation as part of the regular build process.
- Renamed build targetr `gw_codegen` to `cgen`.
- Set default baudrate of UART core to 115200.
- Rewrote Ibex Single Instruction Prefetcher as an FSM.
- Simplified UART and GPIO APIs. The API no longer requires a uart/gpio object.
- Migrated from .c to .cpp.
- Migrated from unsigned to uint32_t/uint8_t.
- Centralized all memory map #defines into memmap.h.
- Put IMEM size in linker script again instead of passing it in via build system. For simplicity's sake.

### Removed
- Removed ad-hoc register map definitions. Replaced with Corsair-generated register map.
- Removed *_flsh software build variant. The bootloader now loads the application image from flash into IMEM.
- Remove arty-a7-35 from Bender.yml files.

https://epsilon537.github.io/boxlambda/minimizing-interrupt-latency-and-jitter/

https://epsilon537.github.io/boxlambda/boxlambda-simplified/…

https://epsilon537.github.io/boxlambda/latency-shakeup/

## Label `boxlambda_base`: Changes Since Label `dfx` - 2025-01-07

### Added

- Support for multiple reconfigurable partitions in the build system.
- Mechanism to acknowledge accesses to invalid addresses and non-responsive slaves, returning a `0xDEADBEEF` data pattern. This feature is enabled in project builds (`boxlambda_base`, `boxlambda_dfx`) and disabled in test builds.
- Invalid Addressing Test Case.
- Second bus master port added to Reconfigurable Partition `VS0`, enabling `VS0` to support a CPU with Harvard Architecture.
- DFX documentation.
- "Official" BoxLambda Project build `boxlambda_base`, which does not support DFX.
- "Official" BoxLambda Project build `boxlambda_dfx`, which supports DFX.
- Gateware build flags: `VS0`, `DFX`, and `ACK_INVALID_ADDR`.
- Two build variants introduced for all software builds: `<sw_project>_ram` (RAM image) and `<sw_project>_flsh` (Flash Memory image).
- `dfx_load_rm()` helper function in `dfx_controller_hal` for loading a reconfigurable module from memory into Virtual Socket 0 (`VS0`).

### Fixed

- Verilator script fails if VERILATOR_CPP_FLAGS not set in Makefile.
- Build trees not clean after running boxlambda_setup.sh.

### Changed

- Renamed IRQ ID and handler for `VS_1` to `VERA`.
- Renamed directory `gw/projects/boxlambda_top/` to `gw/projects/boxlambda_base/`.
- Renamed CMake function `link_and_create_mem_file` to `link_and_create_image`.
- In gw CMakeLists, replaced VERILATOR_CPP_FLAGS and VERILATOR_LD_FLAGS parameters with a single VERILATOR_FLAGS multi value parameter. 
- Instead of relying on a VIVADO_FLAGS environment variable, vivado is now invoked through a wrapper script: *scripts/vivado_wrapper.sh*. The script defines the vivado flags to use.
- Moved all verilator build artifacts except the *Vmodel* executable to a *verilator/* subdirectory of the gw project build directory.

### Removed

- Placeholder IRQ ID and handler for `VS_2`.
- ICAP IRQ handler.
- Deprecated support for the Arty-A7-35T platform.
- Ncurses dependency.

https://epsilon537.github.io/boxlambda/dfx/

https://epsilon537.github.io/boxlambda/i2c-and-rtcc/