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Video of operation
01/02/2017 at 13:13 • 0 comments -
About complete
01/02/2017 at 01:59 • 0 commentsI'm just about completed with the project. I was able to make it stereo while keeping the 32khz sampling rate @ 8 bits.
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Had to scale back the project
01/01/2017 at 15:20 • 0 commentsUnfortunately, I do not have enough time to complete the project by the Jan 5 < 1k challenge date so I must change the scope of the project so that I can complete.
The intent of this project was to create a Class D amp from an ATtiny85 using FILTERLESS (0% PWM at rest) topology; however, I'm having trouble with distortion at the zero cross, and I don't have enough time to diagnose and fix this issue.
I will be changing the scope of the project to use standard Class D methods (50% @ rest) which will require a filter on the output end. :(
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The dreaded zero cross
12/31/2016 at 12:22 • 0 commentsWell, I've run into the same issues I was having with the project from 2014. I don't know if it's related to switching times, but when the PWM crosses from positive to negative, there seems to be a good deal of distortion, and the audio quality suffers at lower volumes.
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Rev 2
12/30/2016 at 18:54 • 0 commentsMade some rookie mistakes on the design of the first board. I could have added a rats nest to the first PCB, but decided to run off another one. Programming starts tomorrow!