Sesenta: Open source tileable acoustic camera

New controller board still at JLPCB, so for now follows a test of one microphone from a Redpitaya which uses the same zynq7 fpga 

Testing steps from Vivado

1. Generate clk for microphone (from Xilinx PLL clk generation with counters, this is required as the PLL itself does not allow slow speeds, in this case 2.4 Mhz)

2. Get the mic data to the CIC compiler ip core as decimator

3. Send decimator mic data to BRAM

4. Read BRAM from linux and put it in a socket

5. Display in python 

Hardware files released

Microphone array (KiCAD)

https://github.com/Iari-Lab/open_acoustic_camera/tree/main/pcb/mic_array

FPGA controller (KiCAD)

https://github.com/Iari-Lab/open_acoustic_camera/tree/main/pcb/controller_zynq

Two versions of the microphone Array have been tested, the latest version is ready for production (KiCAD files in the repo).

The second version of the controller card is being assembled, we hope to test it soon (KiCAD files in the repo).

We are  using an implementation of CIC filters [1] within the FPGA (code based on Matrix Voice HDL [2])

[1] https://en.wikipedia.org/wiki/Cascaded_integrator%E2%80%93comb_filter

[2] https://github.com/matrix-io/matrix-voice-fpga

The initial software tests utilize ODAS for sound source localization [3]

[3] https://github.com/introlab/odas

The  license for software is GNU General Public License v3.0

The  license for hardware  is CERN Open Hardware Licence Version 2