Applix 1616

I made very small milestone in my quest. I have created the equation In WinCUPL with inputs 30Mhz and 15Mhz and generated 7.5Mhz, 3.75Mhz and 1.825Mhz. Put JED file into spare GAL16V8 with GALEP-4 (amazing that thing still works). And bang it works Yes!.

Now on to the next stage put all the other signals in on this Timing PAL.

In the previous picture, I have made some errors on the analyser labels. I have removed the reset signal, i have run out of analyser inputs. I tied it to VCC not needed at this stage. I have been focusing on clock signal.

An interesting thing is the 1.825Mhz is out of phase with 3.75Mhz clock. All other clocks seems to clock on the rising edge.

I am will try and see if I can make the equation and simulate that with WinCUPL.

I used the Analog Discovery 2 to Power the PAL and send signal to inputs and read the output of the PAL.

I start to decode the U51 TPAL2 PAL16R8 today.  Made an interesting discovery, I notice that the RAM CASL and CASU signals are swapped. Scratching my head, thinking why ?.

This must have been a slight design error and the designer decided to correct the error within the PAL. So the UDS signal turns into CASL and LDS  is CASU.

Here is a quick snap shot of signal don't panic the timing is not correct, I stimulated the clock signals with the logic analysers wave generator. More to come.