It's time to come back to this project.

1. The #YGREC8 project must move forward and the DTAP is a blocking, essential sub-unit.
2. The #YGREC32 recently started and a compatible interface (and framework) is a must.
3. A pair of papers have appeared in preprint, proposing trees for 128 and 256 nodes (https://doi.org/10.48550/arXiv.2405.16968).
4. It's time to write an article or two about hardware stuff !

Olivier Golinelli contacted me about his latest works being published, based on my article on the same subject. And not only is it time to implement the DTAP to unblock the design of Y8 but the DTAP should be configurable and accommodate various sizes, to fit the YASEP and YGREC32.

...

Now let's reference the existing work that has been done in the #YGREC8 project, here is a copy-paste of the relevant logs list:

4. The YGREC debug system (the debug system is not the DTAP though, but it is the architecture interfaced by the DTAP, guiding its design)
16. Inspect and control the core (a census of the resources to tap into and bring outside through the DTAP interface)
24. Synchronous Serial Debugging (first diagram of the DTAP structure, set as this project's avatar)
25. MUX trees (first synthesis of a ABCE on FPGA)
109. Gray counter (First design of a Gray counter, or how to create a circuit from its output sequence)
110. The art of large MUXes (Tuning MUX64)
111. The first half of the TAP  (de-scrambling the tree permutations and first attempt at the write shift register)
112. Design of a TAP : the SIPO Controller (first view of the write shift register)
113. The TAP's bits counter (preliminary, superseded by TAPv2)
114. The TAP selector (uses ASCII chars for selecting registers)
115. The TAP is coming together (The first overall structure of the modular write structure)
116. TAP summary & protocol  (first chronograms)
117. Trap on instruction (how to detect a given class of instruction is being decoded)
118. The TAP's eXecute module (it gets messy)
119. The TAP crosses 3 clock domains ! (...)
120. TAP v.2  (reboot ! better, smaller!)
122. Updated Gray Counter  (more Gray !)
123. TAP v.2 : where it's going (timings and chronograms)
124. TAP timing & simulation (VHDL details)
125. TAP v.2's selector (better design)
126. TAP pins (external interfacing)
127. A tale of Flip-Flops  (technical)
136. Tri-mode TAP (continues 126.)
.

However now I remember why DTAP has stalled : it relies on a new unfinished feature of #Libre Gates(enabling asynchronous logic) that required too much work at the time.