DL101
In the current concept, the interface consists of
-USB to Serial converter for basic communication
-6800/6500 series bus, which is also Intel 8000 series compatible. The bus is intended to be used to add extra peripheral devices, such as faster USB I/O interfaces, GPIO interfaces, etc...
-Four input interrupt lines for various hardware
-Support for FT245 (FIFO buffer status lines)
-I2C bus for I2C devices that might be used
-Current DAC, which can also be converted in a voltage DAC
-ADC with a input amplifier which gain can be modified
The bus is driven at the clock of 1MHz, which is actually adequate for this prototype, since the FT245 maximum transfer rate is similar.
At the moment for generating the two phase clock an old MC6875 clock gen IC from Motorola is being used, but that should be replaced when switching to a larger PSoC device, one that has more logic cells, and more I/O pins.
AVR
Michal
Colin O'Flynn
Ralf Messerer