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Restructuring the instruction bundles

A project log for YGREC32

because F-CPU, YASEP and YGREC8 are not enough and I want to get started with the FC1 but it's too ambitious yet.

yann-guidon-ygdesYann Guidon / YGDES 12/07/2024 at 04:010 Comments

I was very satisfied with my instruction-to-pipeline mapping, with one opcode for each globule followed by a control instruction. And today my ideas wandered somewhere else : what about the predicated instructions ?

Due to the still high cost of dealing with branches, it would be awesome to be able to simply "selectively skip" a (small) number of instructions. And this creates a whole lot of new issues, but this is required to reduce the overhead of small branches, due to the still small number of branch target slots.

First, how many instructions is it possible to skip ?

I'd say : not more than a cache line. That's 8 instructions, or 3 cycles at full bandwidth.

This can create some atomicity issues, particularly during decoding. And this also reshuffles the instruction bundle with the predicate in the first/leading position instead of the last.

The point of predication is to conditionally "abort" instructions by preventing the result(s) from being written back to the register set. Otherwise, we're entering the "shadow register hell" and blow up the core's complexity. This also means that predicated instructions can not reuse earlier results from the same predicate. This also implies that control instructions can't be predicated, and maybe no more than 4 ALU operations shadowed (2 cycles get us to the ALU result, it's time to make sure the result is written back, or not).

OTOH this gives just enough time for the control circuits to fetch the relevant condition and propagate the decision.

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BTW the predicated sequences work in a way similar to the "critical section" instruction so there is something to explore deeper here.

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