Historical Ethernet (10Base-T) and Fast Ethernet (100Base-TX) are traditionally working with a serial datastream.

In 100Base-TX, the data are brought in 4-bit nibbles (25MHz), transformed to 5-bit groups which are serialised and from there, scrambling, NRZI and MLT-3 are done purely serially. It's simple and easy, first because "it uses few gates" (particularly for a pre-Y2K technology) and there was not much to do anyway. Baseline wander didn't even seem to be a concern after all.

I could implement the PEAC part with a pair of serial adders and shift registers but this would not bring any advantage, particularly when what people desire is speed. There is a thirst of even higher rates and CRCs keep being used, but how do you run one at 25GHz without crazy silicon technologies? Do you really need to use SiGe, BiCMOS, AsGa, InP ?...

The solution of course is to do as much as possible in the parallel, slower domain, and relegate the serializer to the very last step.

One scaled-down example is the old Actel ProASIC3 FPGA that is rated for a maximum clock speed of 350MHz but has pins that can reach 700M baud using DDR/dual edging. So one clock cycle transfers 2 bits. And even then, the FPGA fabric can't work at such a speed: the adder would work at 100MHz at best.

However if the adder provides the 16+2 bits at once, the frequency is reduced to 39MHz. The high-speed design effort is moved to the high-speed parallel-to-serial circuit. This approach is scalable to other FPGA and even ASIC.

Hopefully it is even possible to preprocess the data to reduce droops.