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Edgi-Talk

Edgi-Talk is a hardware-software collaborative platform designed for chip evaluation, secondary development, and product prototype design. I

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Project Overview
Edgi-Talk is a hardware-software collaborative platform designed for chip evaluation, secondary development, and product prototype design. Its goal is to accelerate the entire development process from functional validation to mass production.
Edgi-Talk integrates a 2.5D GPU and high-bandwidth MIPI-DSI interface, capable of driving high-definition displays and rendering complex graphics, effectively reducing the main processor’s workload. This makes it suitable for embedded applications requiring smooth human-machine interactions. The platform also features rich peripheral interfaces (ADC/DAC, USB, CAN FD, etc.), low power consumption design, and Wi-Fi/Bluetooth connectivity, providing strong support for IoT, smart home, wearable devices, and industrial edge computing applications.

Project Innovations

  • Dual-core heterogeneous architecture combined with hardware NPU, enabling parallel processing of AI and control tasks.

  • Integrated 2.5D GPU and MIPI-DSI interface to meet high-performance graphic display needs.

  • Built-in Wi-Fi + BLE dual-mode communication module, supporting multiple IoT connectivity methods.

  • Native RT-Thread OS adaptation with graphical configuration tools, lowering development barriers.

  • Pre-installed AI dialogue model "Xiao Zhi," enabling instant edge AI human-machine interaction experience.

  • Supports low-power operation, ideal for battery-powered and power-sensitive scenarios.

Why this Project Was Created
With the growth of edge computing and smart terminals, embedded AI systems now require higher performance in terms of computation power, energy consumption, connectivity, and graphical interaction. Traditional MCU platforms face computational bottlenecks in areas like graphic display and AI inference, making them unsuitable for next-generation intelligent applications. The creation of Edgi-Talk is aimed at solving these limitations and providing developers with a one-stop, highly integrated embedded AI development solution.

Problems Addressed by This Project

  • Solving the computational power limitations of traditional MCU platforms for AI tasks.

  • Reducing the resource load of high-performance graphic rendering on the main CPU.

  • Breaking the integration barrier between AI algorithms, system control, and display interaction.

  • Shortening the development cycle from prototype to mass production.

  • Providing out-of-the-box AI voice interaction capabilities to enhance user experience.

    Technical Architecture
    • Processor Architecture: PSoC Edge chip based on dual-core Cortex-M55 + Cortex-M33 architecture, with a built-in neural network processor (NPU).
    • Graphics System: Integrated 2.5D GPU + MIPI-DSI interface, supporting high-definition display output.
    • Communication Capabilities: Built-in Wi-Fi and BLE modules, compatible with IoT communication protocols.
    • Software Platform: RT-Thread embedded operating system + graphical development tools + official reference designs.
    • AI Capabilities: Built-in "Xiao Zhi" large language model dialogue engine, supporting local voice recognition and interaction.
    Workflow
    1. Boot the RT-Thread system and complete peripheral initialization.
    2. NPU supports AI model loading and voice inference processing.
    3. Cortex-M55 handles graphic rendering and AI computation; Cortex-M33 manages peripheral control and low-power management.
    4. GPU outputs graphics to the MIPI-DSI interface for UI display.
    5. Bluetooth/Wi-Fi connects to the IoT cloud platform for remote control and data synchronization.
    6. Use graphical tools for system configuration, debugging, and algorithm deployment.

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Portable Network Graphics (PNG) - 10.15 MB - 09/28/2025 at 03:53

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Portable Network Graphics (PNG) - 5.13 MB - 09/28/2025 at 03:53

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JPEG Image - 7.56 MB - 09/28/2025 at 03:52

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  • 1
    Step 1
    T0 - Requirements DefinitionCompleted platform design goals and core architecture planning.
    T1 - Hardware ImplementationCompleted PSoC Edge mainboard design and functional validation.
    T2 - Software IntegrationPorted RT-Thread, driver adaptation, and pre-installed Xiao Zhi dialogue system.
    T3 - Sample DevelopmentCompleted multiple application reference designs (voice assistant, HMI design, etc.).
    T4 - Release/OptimizationOpen-sourced reference designs, released SDK documentation, and built community support.

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