Netlist_UI.tel

Electrical netlist exported from EasyEDA Pro for the UI board schematic (Rev. Nov 2025).

plain - 37.62 kB - 11/03/2025 at 14:06

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Netlist_Main.tel

Electrical netlist exported from EasyEDA Pro for the Main board schematic (Rev. Nov 2025).

plain - 7.40 kB - 11/03/2025 at 14:05

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BOM_UI.csv

Bill of Materials for the current POC UI board. Includes all ICs and passive parts.

Comma-Separated Values - 15.29 kB - 11/03/2025 at 10:45

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BOM_Main.csv

Bill of Materials for the current POC Main board. Includes all ICs and passive parts.

Comma-Separated Values - 10.98 kB - 11/03/2025 at 10:45

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Darsana_SpecSheet.md

Full hardware and system specification for the Darsana Pico 2 synthesizer.

text/markdown - 6.16 kB - 10/18/2025 at 18:32

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darsana_pinmap.md

Pin assignment map for the Darsana synthesizer (Pico 2 based)

text/markdown - 4.21 kB - 10/18/2025 at 18:31

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Main_board_Schematic.pdf

Complete schematic for the Main & IO board (Rev. Nov 2025).

application/pdf - 635.71 kB - 10/18/2025 at 18:31

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UI_board_Schematic.pdf

Complete schematic for the UI board (Rev. Nov 2025).

application/pdf - 2.95 MB - 10/11/2025 at 15:33

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darsana_panel_design.svg

Front panel layout with 64 knobs and 32 buttons. Designed for 312.6 × 221.2 mm enclosure.

image/svg+xml - 24.52 kB - 10/10/2025 at 12:34

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