Project Logs

Collapse

• A New Direction: A Corrected Forward-Euler Ladder, 4× Oversampling, and Built-In FX

  Hiroyuki OYAMA • 05/08/2026 at 07:34 • 0 comments

  I have made a major change in the DSP direction of Darśana.

  In my measurement bench, I found a new way to compensate for the discretization errors of a forward-Euler ladder filter; especially cutoff tuning and resonance behavior near the high-frequency range.

  With this correction, the forward-Euler ladder now performs at a level comparable to, and in some cases better than, my previous TPT/bilinear ZDF ladder implementation in my measurement bench.

  The important result is simple:

  I can now get a more analog-like sound from a much lighter ladder structure.

  This changes the design trade-off significantly. Instead of spending most of the CPU budget on a heavy zero-delay feedback ladder, I can use a corrected forward-Euler ladder core, run the nonlinear filter section at 4× oversampling; 192 kHz internally; and still have room for more musical features.

  Core 0 is fully dedicated to the main synth engine:

  • 5-voice polyphony
  • 3 oscillators + noise per voice
  • corrected nonlinear 4-stage ladder filter
  • 4× oversampled filter processing

  At the same time, I have started using Core 1 for built-in stereo effects. The current firmware now includes chorus and delay running alongside the main synth engine.

  The result is a richer, wider, and more analog-like sound than before, while still running on the Raspberry Pi Pico 2 / RP2350.

  Please listen to how far this little microcontroller can be pushed.

• Verifying Resonance Consistency in the Ladder Filter

  Hiroyuki OYAMA • 02/06/2026 at 10:45 • 0 comments

  
  I ran a detailed frequency response measurement of the ladder filter implemented in my synth, focusing on two specific properties.

  First, the resonance magnitude remains consistent across the entire frequency range.

  Increasing resonance does not introduce frequency-dependent gain variation, the peak height stays uniform as the cutoff moves. This confirms that cutoff and resonance are effectively orthogonal.

  Second, the resonance peak frequency closely matches the theoretical prediction derived from the linear analog ladder model. The measured peak shift aligns almost perfectly with the analytical reference curve.

  In other words, the digital TPT/ZDF implementation reproduces both:

  • constant resonance magnitude behavior
  • correct analog peak frequency shift

  Above roughly 12 kHz, minor roll-off and deviation appear due to numerical stability limits (fs/8 constraint), but within the practical audio range the behavior remains consistent and predictable.

  With these results, I can confidently rely on this filter design, not only musically, but also from a physical and analytical standpoint.

• Back to a true ladder: non-linear saturation, true zero delay feedback

  Hiroyuki OYAMA • 01/16/2026 at 08:24 • 0 comments

  After an earlier optimization pass, I temporarily switched Darśana’s filter to a simplified / lightweight structure to free up CPU and keep the whole engine stable while I iterated on the rest of the system.
  

  Since then, I’ve gone back and implemented what I actually wanted at the heart of the synth: a nonlinear topology-preserving transform (TPT) ladder filter with zero-delay feedback on the RP2350 - no delay at all in the feedback behavior.

  What changed

  • From: a simplified, lighter filter using hard-clip-style linear saturation
  • To: a TPT/ZDF ladder with nonlinear saturation, where the feedback is solved with zero delay - no delay at all, not even a half-sample delay

  Why I changed it

  I changed it because I didn’t like how the previous approach behaved when driving the filter hard. With high input gain, the waveform would “kink” and fold in a way that felt too abrupt. What I wanted instead was the smoother, more organic kind of compression you hear in real analog circuits — where it squashes gradually rather than snapping into a bend.

  In my view, what most strongly separates analog from digital in this kind of synth filter is (1) how it distorts when driven hard, and (2) aliasing artifacts. Getting the “right” kind of saturation at high input levels is one part of it — but keeping the digital side clean from foldback is just as important.

  On the oscillator side, I also moved to a 4th-order PolyBLEP for anti-aliasing. This more aggressively suppresses the foldback components that people notice most — especially the aliases that fold down below the fundamental, which tend to read as obviously “digital” compared to higher-frequency spurs.

  Current synth load (still on RP2350)

  I’m currently running 5-voice polyphony, and each voice is 3 oscillators + noise → nonlinear TPT/ZDF ladder. The RP2350 definitely has constraints, but it can still run serious, high-quality VA synthesis on real hardware.

• Built-In OLED Oscilloscope & Spectrum Analyzer

  Hiroyuki OYAMA • 01/06/2026 at 11:58 • 0 comments

  I just added two new visualization tools to Darśana’s OLED UI: a tiny oscilloscope and a spectrum analyzer.

  They’re mostly “cosmetic” features, but during development I kept having to power up and connect an external scope (and then re-route cables, re-trigger, etc.). It was annoying enough that I decided: why not put the scope on the synth itself? Now I can sanity-check waveform shape, clipping, and spectral balance instantly — no bench setup required.

  And yes… it’s kind of cute.

  
  

  Bonus: “nonlinear ramp” saw (Model D-ish)
  

  One fun discovery while staring at waveforms: many real analog synth waveforms aren’t perfectly straight ramps. Because of things like capacitor charge/discharge behavior and other non-idealities, the “saw” slope can have a slight curve.

  So I implemented a nonlinear ramp saw inspired by the Moog Minimoog Model D waveform. Visually, it definitely looks more “analog” than a perfectly linear ramp — but honestly, I’m not sure I can hear the difference in isolation.

  Can you? If I upload a short clip, would you be able to pick it reliably?

• Pushing the RP2350 to the Limit: 5-Voice Polyphony with a Non-linear TPT Ladder Filter

  Hiroyuki OYAMA • 12/25/2025 at 06:14 • 0 comments

  I just hit a performance milestone on Darśana: on a Raspberry Pi Pico 2 (RP2350 @ 204 MHz), running on Core 0 only, I’m now running a 5-voice poly engine built from 3 oscillators + noise + a TPT ladder filter per voice — that’s 15 oscillators, 5 noise sources, and 5 TPT ladder filters in total — while keeping peak CPU usage under 90% and staying stable (no dropouts).

  I chose TPT for a simple reason: I wanted a musical, high-quality ladder filter at the heart of the synth. A ladder filter is where a synth’s character often lives — that smooth “grip” when you move the cutoff is a big part of what makes it feel like an instrument. The trade-off is that TPT (especially ZDF-style structures) can be computationally demanding compared to lightweight traditional IIR designs. So I approached it by incorporating as much as I could from guidance in the literature, along with general real-time DSP optimization techniques, aiming to keep the sound quality while fitting within a realistic CPU budget.

  TPT + ZDF: aiming for “no one-sample delay” behavior

  By using a ZDF (Zero-Delay Feedback) TPT structure with trapezoidal integration, the filter stays stable and “analog-like” even under aggressive cutoff modulation, without the thinness you often get from naïve digital structures.

  Key speedups

  To reduce real-time cost, I applied these optimizations:

  • Non-iterative PWL solver (no Newton iterations): Instead of heavy iterative solvers, I use a piecewise-linear (PWL) approach that resolves the saturation characteristic (hard-clipper style) in a single algebraic step.
  • Division-free inner loop: Any per-sample division is eliminated: reciprocals like inv_denom are computed at the control rate, so the audio loop is dominated by multiplications.
  • Efficient 2× oversampling with IIR: To mitigate aliasing from nonlinearities, I use 2× oversampling, but with a 4th-order (2-biquad) IIR instead of FIR, achieving strong attenuation with far fewer cycles.
  • Full unrolling + register-friendly state: The 4-stage ladder is unrolled and internal states are kept as locals to maximize time in registers, minimizing memory traffic and loop overhead.

  Hardware-aware optimization: running critical DSP from SRAM to kill jitter

  Executing from flash via XIP can introduce unpredictable latency (cache misses → jitter). Audio needs deterministic timing, so:

  • I mark time-critical routines (e.g., filter_process, the PWL solver) with `__not_in_flash_func` and run them from SRAM.
  • This improves determinism under load and helps prevent dropouts even when many peripherals are active.

  It's an analog blueprint running at digital speed.
  

• 5-Voice Polyphony Working (TPT Ladder Filter Chain Tuned)

  Hiroyuki OYAMA • 12/24/2025 at 10:26 • 0 comments

  I tuned the full signal chain including the TPT ladder filter, and I can now play 5-voice polyphony reliably.

  On the Raspberry Pi Pico 2, core0 reaches up to ~90% CPU usage at peak settings. This is a great milestone: the filter feels stable and musical while keeping the analog-style topology in a fully digital implementation.

  Next step:

  • Polyphonic, multitimbral sequencer support (so multiple parts/voices can be sequenced independently)

• New VA Engine: 3 Oscillators + Noise → TPT/ZDF Ladder Filter

  Hiroyuki OYAMA • 12/22/2025 at 12:08 • 0 comments

  I’m continuing to explore the software side of this project and revisiting the overall signal chain. I realized that, like many classic synthesizers, mixing multiple oscillators first and then shaping the combined sound with a single filter is simply easier to work with.

  So I reworked my synth’s signal path and replaced the engine with a more traditional VA structure: three oscillators + noise feeding a single ladder filter.

  In parallel, I’ve been working on a TPT/ZDF ladder filter. It’s computationally expensive, but the result is worth it—the filter sounds great, stays stable at high resonance, and handles aggressive parameter changes smoothly.

• First PCBs Arrived and Fully Tested

  Hiroyuki OYAMA • 11/28/2025 at 04:36 • 0 comments

  After a long pause, here’s an update on the hardware progress.

  I’ve received the first batch of PCB/PCBA and finished testing all the major components on the board.

  To my relief, every subsystem — the ADC/knob matrix, LED chain, OLED display, FRAM, and I/O expanders — is working exactly as intended.

  One of my biggest concerns was ADC noise, but in practice it appears to be within a very comfortable range, so that was a nice surprise.

  There was one minor issue: the audio output noise floor is a bit higher than I expected. It’s not severe, but I’d like to improve it in the next hardware iteration.
  

  For the DAC path, I ended up writing a custom I²S Standard 24-bit PCM DMA streamer for the PCM5122.

  Originally I planned to integrate this into the pico_audio library, but that approach required too much overhead, so I opted for a lightweight, dedicated implementation.

  For a quick sound check, I generated a simple saw wave on six instances, tuned them slightly apart, and stacked them into a unison tone. Nothing fancy yet, but it’s a solid first sound coming from this board.

  More updates to come as I move into the next iteration.

• First enclosure render

  Hiroyuki OYAMA • 11/15/2025 at 16:39 • 0 comments

  I’ve been working on the sheet-metal enclosure for Darśana.
  

  This is my first proper attempt at modeling the case in Autodesk Fusion, and it took me much longer than expected.

  Even something as simple as “a box with holes” turned out to involve lots of details—sheet-metal rules, bends, corner seams, offsets, and so on.

  After many trial-and-error cycles, I finally managed to produce a rough top-panel render that includes all the openings:

  potentiometers, keys, the OLED window, and the rear connectors.

  It’s still very much a draft, and I’m sure I’ll revise most of it once I start checking clearances and mechanical tolerances.

  But for now, I’m just relieved that the basic shape is in place.

  More refinements will follow as I get more comfortable with Fusion.

• Survived the DFM gauntlet

  Hiroyuki OYAMA • 11/01/2025 at 16:49 • 0 comments

  I ran exhaustive checks using JLCPCB’s online DFM tool and revised the design until it was fully manufacturable for both PCB and SMT assembly.

  Some traces were redrawn to flow more naturally, some issues were patched or adjusted with minor compromises, and a few alignments had to be intentionally broken to make things fit.

  All major risk points (Dangers) have been cleared, and the remaining Warnings are within acceptable limits for production.

  After going through this process, the overall routing feels cleaner, and the entire circuit design now looks more coherent and balanced.

View all 19 project logs