RISC-4

A 4-bit RISC architecture exploring the question: "What if the RISC revolution happened in 1971 instead of 1981?"

Jeremy King

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Description

RISC-4 is a complete load/store RISC architecture with:

4-bit datapath
16 general-purpose registers
20 instructions (fixed 16-bit encoding)
5-stage pipeline design
Flag based branching
This ISA is implemented in silicon as part of the 4004-recreation project.