Just merged a major release. It achieves timing at a 50mhz with full 68882 feature set including 2 concurrent operations. It has been tested on a custom EMUTOS build on an ALINX ZynqMP build. More details to follow. The LITE 68040 subset is also now available at 50mhz.

MC68881/82 FPGA — CIR Coprocessor Interface Update

What's New

This update brings the FPGA's Coprocessor Interface Register (CIR) protocol in line with the real MC68881/82 hardware
encoding, fixes several bus interface bugs, and adds a comprehensive hardware diagnostic test.
It has also been tested in hardware using a custom EMUTOS build running existing FPU .prg tests. Next release will add SFP004 compatibility

MC68881 Native Opcode Encoding

The CIR command word now uses Motorola's native opcode encoding directly — the same encoding a real MC68020/030 CPU
sends over the coprocessor bus. Previously the FPGA used an internal numbering scheme that required a software
translation layer. This means:

- FMOVE = $00, FSQRT = $04, FSIN = $0E, FADD = $22, FMUL = $23, FDIV = $20, FSUB = $28 — exactly as documented in the
MC68881 User Manual
- The translation switch in the F-line handler has been eliminated
- Software that talks directly to the CIR registers (like Atari TT FPU test utilities) can use standard Motorola
opcodes without any remapping

CIR Bus Interface Fixes

- 32-bit operand transfers: Fixed a bug where long-word writes to the CIR operand register were split into two 16-bit
writes by the emulation layer, causing the FPU to receive zero instead of the actual value. Operand transfers now go
through as single 32-bit AXI transactions, matching real hardware behaviour.
- 68882 pending instruction pipeline: Fixed a race condition where back-to-back instructions could lose the second
operation if its OpWord arrived while the first was completing. The pending instruction flags are now only cleared
when actually consumed.

Hardware Diagnostic (cirtest)

New standalone 68K test program (cirtest.c) that exercises the full CIR dialog protocol from the Merlin2 monitor. Runs
12 tests covering:

- Integer load/store round-trips (positive and negative)
- Memory-to-register arithmetic: FADD, FMUL, FDIV, FSUB
- Register-to-register arithmetic: FADD FPn,FPm
- Unary operations: FSQRT, FNEG, FABS
- Double-precision transcendentals: FSIN(1.0), FSQRT(2.0)

All 12 tests pass on hardware. All 13 GHDL simulation testbenches pass.

Known Issue: SFP004 Peripheral Protocol

Disassembly of FPU_HARD.PRG (Quidnunc 1991, commonly used on Atari ST/SFP004 boards) revealed it uses a different
register protocol than the MC68020 CIR standard — it writes commands without an OpWord and expects different response
encodings. This will be addressed in the next update to support the SFP004 peripheral access pattern alongside the
standard CIR protocol.

Files Changed

19 files across VHDL RTL, testbenches, C firmware, and documentation. No changes to the ALU computation logic — only
the bus interface encoding and protocol handling.