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• The 6-Month Silence: What Actually Happened

  Masahiro Furukawa • 3 days ago • 0 comments

  Six months after freezing our initial V0 prototype, real-world networking, bootloader hacks, and an unexpected fit with the Raspberry Pi Zero transformed ADX from a single rugged board into a 3-Tier open hardware standard for enclosure-native modular electronics.

  The 6-Month Silence: What Actually Happened

  Back on April 30th, we posted our last project log announcing that the schematics for ADX Core V0 were frozen and sent off to JLCPCB.

  And then... total silence for nearly six months.

  We didn't abandon the project. Quite the opposite: once the physical boards arrived on our bench and we started debugging, everything looked great. But the moment we tried to actually design an enclosure for it—and started seriously planning how it would connect to messy, real-world factory wiring—we hit a massive wall.

  It turns out, making a board work on a desk is easy. Designing a board that makes sense inside an industrial enclosure, handles external wiring cleanly, and remains maintainable is a completely different beast.

  What started as an effort to build "a rugged industrial Arduino on an ATtiny1616" had to fundamentally transform. Over the past half-year of staring at CAD models, realizing our initial architecture wouldn't survive outside the lab, and doing stripped-down redesigns, ADX has evolved into something much broader: The Open Hardware Standard for Enclosure-Native Modular Electronics.

  Here is the lab notebook on how we hit the "enclosure wall," what we re-engineered, and where the standard stands today.

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  1. Networking in the Real World: The Core-D Experiments

  When the V0 boards landed on our bench, basic GPIO toggles worked fine. But our ambition was multi-drop industrial communication: daisy-chaining multiple boards over a single twisted pair with robust bootloading.

  Fig 1: Two ADX Core-D prototypes on the bench running half-duplex RS-485 packet transmission experiments.

  To rigorously test field protocols, we designed and spun a dedicated testbed board: ADX Core-D. Starting in late August, we iterated through several protocol layers:
  - LN-485 (LIN-based packet frames over half-duplex RS-485)
  - PAL (Physical Access Layer tuning, slew-rate shaping)
  - DROP-BUS (Collision handling and deterministic multi-drop streaming)

  Fig 2: Three ADX Core-D boards stacked in a 3-tier cascade for multi-node data streaming and bus arbitration stress tests.

  Running continuous data streams across three cascaded boards revealed crucial lessons about ground-bounce, common-mode noise, and line reflections. It quickly proved that robust galvanic isolation wasn't just a nice-to-have spec sheet bullet—it was an absolute requirement for survivable field hardware.

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  2. The Field Maintenance Dilemma: WebSerial & OTW Bootloading

  The biggest operational pain in embedded field deployments is simple: nobody wants to drag a heavy laptop and a dedicated hardware debugger (like a UPDI dongle) up a ladder or into a dusty electrical cabinet just to tweak three lines of code.

  We wanted OTW (Over-The-Wire) firmware updates over the existing RS-485 bus, controllable directly from a standard web browser via the WebSerial API.

  In late September, we built and deployed a browser-based WebSerial PWA Uploader (hosted directly on our GitHub Pages). But we immediately ran into a notorious low-level barrier:

  Standard USB-to-UART bridge chips (CH340, FTDI, CP2102) and operating system drivers (especially Windows Win32 serial drivers) handle standard send_break() signals unpredictably. Pulse widths varied wildly from a few milliseconds to over 100 ms, completely desynchronizing the target bootloader.

  The Hack: The Half-Baud Pulse Trick
  Instead of relying on fragile OS break APIs, we developed a deterministic timing workaround: temporarily cutting the baud rate in half and transmitting a framing pattern (or injecting a calibrated zero byte at the lower baud).

  This simple software hack generated a rock-solid, predictable break pulse across...

  Read more »

• ADX Core V0 Design Freeze and PCBA Order Placed

  Masahiro Furukawa • 04/30/2026 at 15:16 • 0 comments

  Progress Report: ADX Core V0 Design Freeze and PCBA Order Placed

  The design phase for the ADX Core V0 is officially complete. I have finalized the schematics and PCB layout, and the project has moved into the manufacturing stage. The PCBA (Printed Circuit Board Assembly) order has been placed with JLCPCB.

  Status Update

  • Schematics: Completed
  • PCB Layout: Completed
  • Manufacturing: In progress (Ordered via JLCPCB PCBA service)
  • Target Grade: Industrial / Robust Control

  Project Resources & Documentation

  All design files, fabrication data (Gerbers, BOM, CPL), and detailed development history are available on GitHub:

  Repository:

• https://github.com/Masafuro/ADX/

  Note: The repository contains documentation and commit messages in a mix of English and Japanese.

  Hardware Specifications

  The ADX Core V0 is designed as an "Arduino-like" industrial control board. It introduces a new, standardized industrial form factor—inspired by the ATX philosophy—aimed at creating an ecosystem where enclosures and components are easily interchangeable and professional.

  1. Performance Specifications

  Item	Specification	Notes
  MCU	Microchip ATtiny1616-MNR	8-bit AVR® megaAVR 0-series
  Clock Speed	20 MHz (16 MHz recommended)	Internal clock
  Logic Voltage	5 V
  Memory	Flash 16 KB / SRAM 2 KB / EEPROM 256 B
  Operating Temp	-40°C to +105°C	Industrial grade components

  2. Power & Protection

  Item	Specification	Notes
  Nominal Input	DC 12 V / 24 V / 48 V systems
  Input Range	DC 7.0 V to 48.0 V
  Protection	SMD Chip Fuse / Reverse Polarity
  Surge Protection	TVS Diodes	Mounted on power input
  Connection	2-pin Push-in Terminal	Pluggable with lock lever

  3. Communication & Interface

  Item	Specification	Notes
  Protocol	RS-485 x 1 channel
  Protection	TVS Diodes	A / B line protection
  Programming	UPDI	3-pin socket (UPDI, VDD, GND)

  4. GPIO Pin Assignment

  Connector: 2×10 pin Locked IDC Box Header (Right Angle)

  The layout utilizes multiple GND and VDD pins to ensure signal integrity and stable wiring in industrial environments.

  Pin	Signal	Notes	Pin	Signal	Notes
  1	VDD	5V Out	2	GND	Ground
  3	PC3	GPIO	4	PC2	GPIO
  5	PC1	GPIO	6	PC0	GPIO
  7	GND	Ground	8	PB0	GPIO
  9	PB1	GPIO	10	PB2	GPIO
  11	PB3	GPIO	12	GND	Ground
  13	PB4	GPIO	14	PB5	GPIO
  15	GND	Ground	16	PA7	GPIO
  17	PA6	GPIO	18	PA5	GPIO
  19	GND	Ground	20	VDD	5V Out

  5. Mechanical Specifications

  • Dimensions: 85.0 mm × 60.0 mm
  • Mounting: 4 x M3 screw holes (corners)
  • Features: 8.0 mm washer clearance, C3 chamfered edges.

  Next Steps

  Once the boards arrive from the fab, I will proceed with:

  1. Power rail verification: Testing stability with 24V and 48V inputs.
  2. Firmware upload: Initializing the ATtiny1616 via UPDI.
  3. Stress testing: RS-485 communication reliability in high-noise environments.