Project Logs

Collapse

• Playing with my PALs

  Dave • 2 days ago • 0 comments

  Not having much luck with my new PALs. Getting the right signals out for the clock divisors, RAS and LPULSE are ok butt CASL and CASU are not. Need to check the basics like the HALT signal as well as the BR (Bus Request) and BGACK (Bus Grant Acknowledge). Then the interrupt lines and make sure they are not low for some reason. So a bit of work to understand what's going on.

  Gee I hope this thing can play some good games 😋

• My PALs have arrived!!

  Dave • 3 days ago • 0 comments

  A fellow Hackster gave me the all important Timing and Video PALs for the board. These are quite rare as they can't be read with a simple EPROM programmer so not easily copied. The original program for these has been lost to time so the only way to create new ones is to reverse engineer real ones. While not too difficult it does involve inputting various conditions and see what pops out. The Timing PAL manages the timing for the DRAM refresh and needs to do it in sync with the 6845 CRTC controller. So can be a bit tricky.

  But anyway I stuck them in and no joy the clock divisor works ( pins 17-19 ) and LPULSE (12) but DTACKR and RAS, CASL and CASU all stay high. Haven't had a proper look yet. Still need to do some tracing ( its most likely me not the board) may be as simple as something in the reset circuit. I'm not forgetting about the VPAL but without the timing the VPAL won't be doing much.

  I  have till Friday to sort it out as I promised to lend them to someone in the UK who is lot smarter than be and will be about to sus it out in a jiffy. 

  And this is the pinout for the TPAL.

• Made a start

  Dave • 05/12/2026 at 23:04 • 0 comments

  Have made a start on the board. Was only going to do the minimum to work on the Timing PAL (TPAL) programming. But was in the zone so kept going until I ran out of IC sockets and .1uf Caps. Another order for DigiKey 🫤

  The EPROMs ( sorry FLASH Memory) are programmed with the original code. As for the TPAL I managed to work out the clock divisors, but the TPAL does a lot more than that. It uses a 3-bit synchronous counter driven by 30 MHz and 15 MHz clock inputs to generate critical DRAM timing signals, such as /RAS, /CASL, /CASU, and ROW/COL. Not something I can work out easily so will have to wait for people smarter than me to work that one out.  

  Till then I'll be optimistic and continue soldering bits in. Have a good de-soldering gun as back up. 😋

View all 3 project logs