A custom FPGA system built on the Xilinx Spartan-6 XC6SLX9 chip. The project integrates multiple classic controllers and modules into a single chip, creating a platform similar to a retro computer. The system is written entirely in Verilog HDL and synthesized in Xilinx ISE 14.7.

It provides a complete graphics and I/O platform: VGA output with framebuffer, text and sprite engines, PS/2 keyboard, UART, SD card support, and a custom CPU interface for issuing commands.

ARCHITECTURE

The CPU communicates with the FPGA through a parallel bus with a 16-register memory map (ram[0]...ram[15]). The interface supports two synchronization methods:

- Interrupt-driven mode — the FPGA asserts the INT line when an event occurs (e.g. command finished, UART data received, PS/2 key pressed).
- Polling mode — the CPU periodically reads the status register ram[15] to check flags (busy, data ready, error).

Both methods can be used simultaneously — the CPU can enable only selected interrupt sources via the interrupt enable register, and poll the rest.

FEATURES

Graphics
- VGA Controller — generates standard 640x480@60Hz VGA signals (HSYNC, VSYNC, RGB) using a 25 MHz pixel clock.
- SRAM Framebuffer — external SRAM uses a 16-bit data interface. The framebuffer uses 8-bit RGB332 pixels, with the lower byte (LB) and upper byte (UB) available as separate graphics buffers. The active buffer can be switched by CPU command without stopping VGA display.
- Graphics Commands — CMD_DRAW_LINE uses Bresenham's algorithm to draw lines, with support for line thickness and dashed style. CMD_SET_BUF_LB and CMD_SET_BUF_UB select the lower or upper byte of the SRAM data interface as the active graphics buffer.
- Text Engine — 80x60 character mode with 8x8 pixel font. Supports cursor with adjustable height, color, and blinking.
- Sprite Engine — 8 independent sprites, each 16x16 pixels with 8-bit color. Supports per-sprite transparency (color 0), horizontal/vertical flipping, and enable/disable control.

Input / Output
- PS/2 Keyboard — full bidirectional PS/2 controller. Receives scan codes and decodes them to ASCII. Supports Caps Lock, Num Lock, and Scroll Lock with LED control. Handles extended keys.
- UART — universal asynchronous receiver/transmitter with 5 selectable baud rates: 9600, 19200, 38400, 57600, and 115200 bps.
- SD Card — SD card controller operating in SPI mode. Supports card initialization (CMD0, CMD8, CMD55, ACMD41, CMD58), block read (CMD17), and block write (CMD24).

CPU Interface
- Parallel Bus — 5-bit address, 8-bit data, with CE_n, OE_n, WE_n signals. A bidirectional buffer (ENABLE, DIR) controls the data flow direction.
- Command Interface — 16 memory-mapped registers (ram[0]...ram[15]). The CPU writes command parameters, then writes the command number to ram[0].
- Interrupt System — dedicated INT output line with 8 individually maskable sources: timer overflow, PS/2 data ready, UART RX/TX, command done, and RTS change.
- 8-bit Timer — configurable prescaler and reload value for periodic interrupts.
- Pseudo-Random Generators — 8-bit and 16-bit LFSR.
- Real-Time Clock — Unix timestamp counter (32-bit) with 1-second resolution.

TECHNICAL SPECIFICATION

FPGA chip: Xilinx Spartan-6 XC6SLX9
Package: TQFP-144
Language: Verilog HDL
IDE: Xilinx ISE 14.7
Main clock: 50 MHz
VGA pixel clock: 25 MHz
VGA resolution: 640x480 @ 60 Hz
Color depth: 8 bpp (RGB332)
Text mode: 80x60 characters
Sprite count: 8 sprites, 16x16 px each
Framebuffer: External SRAM, 640x480 pixels, 8 bpp per buffer
SRAM data interface: 16-bit
Graphics buffers: Lower byte (LB) and upper byte (UB)
CPU bus: Parallel, 5-bit address, 8-bit data
Interrupts: 8 sources, individually maskable

VERSION HISTORY

Version 1.1 (2026-10-10)
- Added CMD_DRAW_LINE, CMD_SET_BUF_LB, CMD_SET_BUF_UB
- Expanded SRAM data bus to 16 bits
- Added graphics buffer switching (LB/UB)
- Fixed bugs in thick_step and thick_begin

Version 1.0 (2026-10-06)
- First public release
- VGA, SRAM framebuffer, text engine, sprite engine
- PS/2, UART, SD card...