Command Execution Flow:
1. Write parameters to registers ram[1]...ram[9].
2. Write command number to ram[0] — this starts execution.
3. FPGA executes the command — the busy flag in ram[15] is set.
4. Wait for completion — either poll ram[15] bit 0, or wait for the INT line.
5. Read result from ram[15] (status) or specific registers.

Interrupt Handling:
1. Enable interrupts — write mask to ram[18].
2. Wait for INT — the FPGA asserts the INT line when an enabled event occurs.
3. Read flags — read ram[16] to see which interrupt fired.
4. Handle event — perform the required action.
5. Clear flags — write 1 to the corresponding bits in ram[17].

Full details: https://github.com/rick1961pl-ops/fpga-spartan6-code1