Spartan-6 FPGA Retro System

The atmega_demo-v1.1.zip archive contains CPU-side demo code for ATMega microcontrollers. It demonstrates how to use the buffer switching commands and basic graphics drawing.

Download it from the Files section.

CMD_DRAW_LINE (23) implements Bresenham's algorithm with support for line thickness and dashed style. The command takes 5 parameters: start X/Y, end X/Y, color, thickness, and dash style.

Fixed two bugs:
- thick_step: stray pixels when drawing thick lines — used $unsigned casting instead of truncating the sign bits.
- thick_begin: added clearing of wr_req before starting a new thickness block.

Version 1.1 added graphics buffer switching (CMD_SET_BUF_LB / CMD_SET_BUF_UB). The switching is synchronized with VBlank to avoid tearing — the buffer swap happens only during the vertical blanking interval (v_cnt >= 480).

Implementation:
- Added vblank output to vga_timing.v
- Added ST_WAIT_VBLANK state to cpu_ram.v
- Buffer swap is triggered by rising edge of vblank

This ensures the VGA display never shows a partially-drawn frame.

Project Introduction

This is a custom FPGA system built on the Xilinx Spartan-6 XC6SLX9 chip. It integrates multiple classic controllers into a single chip: VGA (640x480), text engine, sprite engine, PS/2 keyboard, UART, SD card, and a custom CPU interface.

The project is written in Verilog HDL and synthesized in Xilinx ISE 14.7.

Version 1.0 was released on 2026-10-06.
Version 1.1 was released on 2026-10-10 with new graphics commands and 16-bit SRAM buffer switching.