I worked all weekend on figuring out how Vivado timing constraints work. At first it seemed pretty similar to ISE, but I kept getting errors. Apparently there's a lot more to it. Input and output timing constraints seem to be required to eliminate all critical warnings. It's probably to protect against all system level timing problems. I used to just register all inputs and outputs at the pin to minimize timing paths, but I suppose this way could be better to be sure.

After many hours I figured out I had two timing constraints on the clock. I guess the clocking wizard created one which I didn't know about. Now I'm down to just one problem: the 74181 model I found is giving me a circular reference. It's a bit of a mess, so I may rewrite it now that I have a better understanding of how it works. I also haven't fully checked it, so it's possible there's a mistake. I think after I fix that, I'll be able to generate a bitstream and download. We'll see tomorrow.