I should really learn to follow the most basic of guidelines when it comes to digital design.  One of the biggest is "don't gate the clock" which I totally did.  The BREAK output from my ROM is glitching which causes the clock to glitch high for about 200ns.  This causes some chips to clock and some don't.  I can even force this output low on all ROM values, and it still glitches high.  So I can short-term fix this by putting a capacitor on this pin.  Long term I should redesign my clock circuitry and do it right.  But I'm going for short-term fixes for now.

I've also found my reset scheme is even more annoying in that it is synchronous to my control circuit, and asynchronous to my program counter chip.  And then I forget that my control circuit is wired to take an extra clock cycle on startup, but the program counter does not.  So the first instruction will execute at address 0x0001 instead of 0x0000.  I'd prefer to have the first instruction be at 0x0000, so I'm going to try to fix it.  I just have to clock the control logic once and then reset without clocking, and everything is in step.  Again, not a long term solution, but it will work in the short term.

Annoying!