I've made quite a bit of progress building the board.  I fixed the reset issue by changing the load state of the shift register by remove two resistors and changing one to a pull-down.  I soldered on a capacitor to filter the BREAK signal, but I haven't checked if it's too much filtering and disables the functionality at a high clock speed.

I added the instruction ROM, and found another bug.  I needed to bring the most significant bit of the address bus into my control ROM decode to disable the ROM when the RAM is being accessed.  Just one more jumper wire.

I added the Source/Destination circuitry and found another bug.  I have an enable for either the SRC/DST address or the pointer address.  It doesn't disable the output to the memory address bus correctly, but fortunately I have an extra AND gate which I can use to fix it.  But it's one more cut trace and three more jumper wires.

I also didn't update my decoding of the pointer address, so my new address for the pointer data is 0x0004 (it was 0x000B).  Not a big deal, I just have to update my constants in my include files.

I guess this is the price I pay for not prototyping it on a solderless breadboard, but these problems are not huge (yet).