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VHDL
04/20/2017 at 12:44 • 1 commentI decided I'm going to need to simulate this thing first. So I have to get a simulator. I haven't written VHDL in a few years, but it used to be my career focus. So I'm downloading Xilinx Vivado Webpack. I haven't used this before, but I was proficient with Xilinx ISE.
I'd like to have instructions take one clock cycle, but I'm not sure if I can pull that off. I'd also like to have one shared memory. But if I want to fetch instructions and write back to the memory in one clock cycle, then I'll need a dual-port. I don't think I can find a friendly one for breadboarding. So I think I'm stuck with either separate instruction/data memories, or multiple clock cycles per instruction. The timing problems make me uncomfortable enough that I will need to simulate.
I'm also still split on 8-bit memory bus or 16-bit memory bus. If I want to fetch an instruction in one cycle, I need a 16-bit memory bus (two parallel 8-bit chips). I could do two cycle fetch with an 8-bit bus from sequential memory locations, and then one cycle execute, but that'll just slow down execution and take more control resources. So I still have decisions to make on my architecture.
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ALU 54LS181
04/20/2017 at 11:47 • 4 commentsSo I'm already running into difficulties with parts. Fortunately I can dig well and came up with this guy:
http://www.ti.com/product/SN54LS181/description
It's an active 181 ALU. Sure it's the 54181, but it will work just fine. I'm not against the 5400 series. And it makes my life much easier. And it's an active device, so it qualifies. Sure it's just 4-bit, but it's easy to gang them together.
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One or zero?
04/20/2017 at 11:42 • 0 commentsI'm wondering about the difference between a one and zero instruction computer. If there's only one instruction, then isn't it really implied? Wouldn't that make it a zero instruction computer? I guess if I think about it, a zero instruction computer doesn't do instruction decoding - the compiler has direct access to the control signals of the datapath. So that would really be a extremely large instruction set computer - it's just that the instructions are not defined by the hardware but by software. In my computer, only one thing will happen - moving data from one location to another. So I guess I am a one instruction. But I argue there's no such thing as a zero instruction - the instructions are defined by the compiler.
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Inspiration
04/19/2017 at 17:42 • 0 commentsI've found the musical inspiration for my project.
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Bus design
04/19/2017 at 13:30 • 0 commentsThe address/data bus will be the focus of the computer. I will need two address buses - one for the source address and one for the destination address. And I will need one data bus. I figure for now I will keep it simple and have them all be 8-bit buses. This means my instruction memory will be 16-bits wide since each instruction will include both the source and destination addresses.
One reason is that I will need a way to put constants from the program into the data bus. I don't want to create a second instruction which writes a constant into a register because that breaks my #1 goal. So instead I'll need a special function register. In a normal register, when the destination address targets it, it captures data from the data bus and stores it. In this special function register, when the destination address targets it, it captures the value of the source address bus instead.
One thing to consider is how the source address bus works. Since I'm not really using the source address bus as an address and instead as a data word, it could mess up whatever the source address is pointing at. For example, if my data word is 9 and that memory location is a FIFO, a read of that register may pop off the word at the top of that FIFO. I'm not sure how exactly to handle this just yet, but I think I can. I could do a two-step command like disabling the source bus address or something in the first step. I could reverse the command so that the source is actually the destination and put the data word into the destination address. Of course, that just reverses my problem. I'll think on it.